Arteris Articles

Arteris IP Awarded 1st Place for Technical Paper at Synopsys Users Group (SNUG) Silicon Valley 2019

Benny Winefeld, Solutions Architect at Arteris IP, Awarded 1st Place Best Paper Award at SNUG Silicon Valley 2019 

Arteris IP presented this technical paper, "Using Machine Learning for Characterization of NoC Components", on March 20, 2019.

Benny Winefeld, Solutions Architect at Arteris IP, accepted the 1st Place Best Paper Award from the SNUG Technical Committee during SNUG Silicon Valley. There were 29 papers that competed for the best paper award.

In the photo above, Benny receives the award from the SNUG committee, from left to right: Ken Nelson, VP Field Support Operations; Benny Winefeld, Solutions Architect, Arteris IP; Tony Todesco, SNUG SV Technical Chair, AMD; and Deirdre Hanford, Co-GM, Synopsys.

Topics: Synopsys NoC machine learning artificial intelligence Soft IP noc interconnect SNUG

Semiconductor Engineering: What Makes A Good Accelerator

Kurt Shuler, VP of Marketing at Arteris IP, comments on 'What needs to be accelerated' in this Semiconductor Engineering article:

What Makes A Good Accelerator

 

October 25th, 2018 - By Ann Steffora Mutschler

Topics: FPGAs machine learning neural network semiconductor engineering soc architecture arteris ip SoCs

SemiWiki: On-Chip Networks at the Bleeding Edge of ML

On-chip networks become a lot more challenging at the high-end of machine learning (ML). Bernard Murphy (SemiWiki) talked with Kurt Shuler, VP Marketing at Arteris IP, about the experience they have developed over the years of working with well-known ML product builders and how this has influenced  the AI package recently released by Arteris IP in this SemiWiki blog:

On-Chip Networks at the Bleeding Edge of ML 

November 29th,  2018 - By Bernard Murphy

I wrote a while back about some of the more exotic architectures for machine learning (ML), especially for neural net (NN) training in the data center but also in some edge applications. In less hairy applications, we’re used to seeing CPU-based NNs at the low end, GPUs most commonly (and most widely known) in data centers as the workhorse for training, and for the early incarnations of some mobile apps (mobile AR/MR for example), FPGAs in applications where architecture/performance becomes more important but power isn’t super-constrained, DSPs in applications pushing performance per watt harder and custom designs such as the Google TPU pushing even harder.

Topics: SoC NoC FPGAs semiconductor machine learning FlexNoC semiwiki kurt shuler AI chips flexnoc ai package

Semiconductor Engineering: Architecting for AI

Ty Garibay, CTO at Arteris IPparticipated on the "Experts at the Table" at DAC with other industry luminaries for this Semiconductor Engineering article:

Architecting for AI

 

July 7th, 2018 - By Ann Steffora Mutschler

Topics: semiconductor machine learning artificial intelligence semiconductor engineering arteris ip inference thermal envelope constraints interconnects power efficiency