Arteris Articles

SemiWiki: On-Chip Networks at the Bleeding Edge of ML

On-chip networks become a lot more challenging at the high-end of machine learning (ML). Bernard Murphy (SemiWiki) talked with Kurt Shuler, VP Marketing at Arteris IP, about the experience they have developed over the years of working with well-known ML product builders and how this has influenced  the AI package recently released by Arteris IP in this SemiWiki blog:

On-Chip Networks at the Bleeding Edge of ML 

November 29th,  2018 - By Bernard Murphy

I wrote a while back about some of the more exotic architectures for machine learning (ML), especially for neural net (NN) training in the data center but also in some edge applications. In less hairy applications, we’re used to seeing CPU-based NNs at the low end, GPUs most commonly (and most widely known) in data centers as the workhorse for training, and for the early incarnations of some mobile apps (mobile AR/MR for example), FPGAs in applications where architecture/performance becomes more important but power isn’t super-constrained, DSPs in applications pushing performance per watt harder and custom designs such as the Google TPU pushing even harder.

Topics: SoC semiwiki kurt shuler NoC semiconductor machine learning FPGAs AI chips FlexNoC flexnoc ai package

Semiconductor Engineering: Architecting for AI

Ty Garibay, CTO at Arteris IPparticipated on the "Experts at the Table" at DAC with other industry luminaries for this Semiconductor Engineering article:

Architecting for AI


July 7th, 2018 - By Ann Steffora Mutschler

Topics: semiconductor engineering arteris ip semiconductor interconnects artificial intelligence machine learning inference thermal envelope constraints power efficiency

Architecting the Future of Deep Learning

Ty Garibay, CTO of Arteris IP, delivered the Keynote Address, “Architecting the Future of Deep Learning," which discusses the emerging system-on-chip (SoC) architectures enabling artificial intelligence, machine learning, and deep learning and how semiconductor technology can enable these innovations. Ty presented this keynote presentation at the eSilicon ASICs Unlock Deep Learning Innovation Seminar on March 14, 2018.

Topics: eSilicon deep learning machine learning artificial intelligence soc architecture