Ty Garibay, CTO at Arteris IP, authored this Semiconductor Engineering article:
Artificial Intelligence Chips: Past, Present and Future
August 2nd, 2018 - By Ty Garibay
Madelyn Miller, on Thu, Aug 09, 2018 @ 06:00 AM
Ty Garibay, CTO at Arteris IP, authored this Semiconductor Engineering article:
August 2nd, 2018 - By Ty Garibay
Kurt Shuler, on Wed, Feb 03, 2016 @ 10:00 AM
It destroys itself as it is operating.*
Bear with me now as I explain how SSD flash memory works similar to helicopters...
First, let's explain the helicopter part of this analogy: Fixed wing aviators (i.e. non-helicopter pilots) are keen to remind people that the act of converting a jet engine's axial force into the orthogonal axis required to spin a helicopter rotor requires a sophisticated gearbox that slowly (and sometimes not so slowly) grinds itself to death through friction.
Kurt Shuler, on Fri, Dec 18, 2015 @ 04:51 PM
Editor's note: This is a great article by Ed Sperling at Semiconductor Engineering, so I have highlighted it here. Cache coherency in modern SoCs is discussed toward the middle of the article. -Kurt
Read the entire article at Semiconductor Engineering.
NOVEMBER 24TH, 2015 - BY: ED SPERLING
Memory is becoming one of the starting points for SoC architectures, evolving from a basic checklist item that was almost always in the shadow of improving processor performance or lowering the overall power budget. In conjunction with that shift, chipmakers must now grapple with many more front-end decisions about placement, memory type and access prioritization.