Arteris Articles

Semiconductor Engineering: Edge Complexity To Grow For 5G

 Arteris IP's Kurt Shuler, Vice President of Marketing, quoted in the latest Semiconductor Engineering article:

Edge Complexity To Grow For 5G

July 2nd, 2019 - By Kevin Fogarty and Ed Sperling

Increased interdependence of technologies will drive different architectures and applications. 

It gets even more complicated in the automotive world than other any other markets because of safety-critical circuitry.

“You may have to reboot part of the chip for a failed operation, while keeping the rest of it operating in a safe state,” said Kurt Shuler, vice president of marketing at Arteris IP. “If you think about the space shuttle or a Boeing 777, the black boxes are 20 pounds. You can’t have that in a car. There is a lot of functional safety being done at the microprocessor level to save cost. That can be used to spy on what’s happening at the system level, so if there are problems you can isolate them and in a safe state and fail gracefully. If there is a transient error, you reboot.”

For more information, please download the Arteris FlexNoC AI Package data sheet; http://www.arteris.com/download-flexnoc-ai-package-datasheet

Topics: SoC functional safety FPGAs semiconductor engineering flexnoc ai package noc interconnect ML

Semiconductor Engineering: Machine Learning Drives High-Level Synthesis Boom

 Arteris IP's Kurt Shuler, Vice President of Marketing, quoted in the latest Semiconductor Engineering article:

Machine Learning Drives High-Level Synthesis Boom

June 6th, 2019 - By Kevin Fogarty

When a  company puts together a software/hardware design team, it's not a bad idea to make sure where the final responsibility lies.

Asking the right questions
“In China I had a long conversation with the hardware engineer about what we were trying to do, and it eventually became clear he was not the one calling the shots,” said Kurt Shuler, vice president of marketing at Arteris IP. “It was the software architect calling the shots, so we all got together and that let us move forward once I realized the chip was defined by the algorithm, not the other way around.

”But the software architect doesn’t always have a good feel for the hardware. “The other problem we had was that, often, a software architect won’t be that good at abstracting down to the transistor level, and the hardware architect may not be good at abstracting up to the software, so you have to kind of walk them through that,” said Shuler.

Insisting on tight integration and optimization of software with hardware also may be a good way to coordinate development, but it doesn’t always reflect realistic performance requirements. Shuler noted that one way to help customers think about the problem is, rather than asking the hardware architect what would happen if the chip didn’t live up to expectations, to ask what the impact on the device would be if they were to remove the chip and replace it with an off-the-shelf inference chip that would have been completely generic to the application.

For more information, please download the Arteris FlexNoC Interconnect IP data sheet; https://www.arteris.com/download-flexnoc-datasheet

Topics: SoC semiconductor engineering noc interconnect ML software architects

Arteris IP at Synopsys Users Group Silicon Valley 2019


Arteris IP at SNUG Silicon Valley 2019 

Location: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA  
Track: Artificial Intelligence - Wednesday, 20 March, 3:45 pm - 4:30 pm

Arteris IP is presenting this paper, "Using Machine Learning for Characterization of NoC Components"

Topics: NoC semiconductor FlexNoC Soft IP SoCs RTL noc interconnect ML PPA

Semiconductor Engineering: Using AI Data For Security

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments about the edge emerging as a particular security concern because some of the devices can kill you, covered in this Semiconductor Engineering article;

Using AI Data For Security

February 20th, 2019 - By Ann Steffora Mutschler

Pushing data processing to the edge has opened up new security risks, and lots of new opportunities. 

The edge and beyond
“It’s cars and robots and medical devices,” said Kurt Shuler, vice president of marketing at Arteris IP. “These things can kill you two ways. A cosmic ray can cause a bit to flip, and things go awry. The other way is that the AI may work as intended, but what it decides to do from its neural net application is the wrong thing. In that case, the safety of the intended function is bad.”

There’s even a new spec just for this: “ISO/PAS 21448:2019 Road vehicles — Safety of the intended functionality.” That captures how to analyze these AI powered systems going into cars, so they works as designed.

Security can impact all of these systems. “There’s a totally separate set of specs, and a totally separate set of Ph.D. geeks working on safety and on security,” said Shuler. “What’s disconcerting is that the effects of any of these things, especially from a functional safety standpoint and a security standpoint, can be the same. Whether a bit flips or an engineer flipped a bit, someone can get hurt. Yet these sets of experts don’t really talk to each other too much. This was addressed in the new ISO 26262 2018 specification that came out in December, which includes specific text to address this. It basically says you must coordinate with security guys, but unless security is somehow mandated to a certain level — like functional safety is in cars and trains and other verticals — nobody really cares. It’s like insurance. Nobody wants to pay for too much security.”

For more information about ISO 26262:2018 Part 11, please download this presentation "Fundamentals of ISO 26262 Part 11 for Semiconductors".

Topics: semiconductor automotive AI ISO PAS 21448 data centers noc interconnect ML AI SoC Designers ecosystem