Arteris Articles

Semiconductor Engineering: Machine Learning Drives High-Level Synthesis Boom

 Arteris IP's Kurt Shuler, Vice President of Marketing, quoted in the latest Semiconductor Engineering article:

Machine Learning Drives High-Level Synthesis Boom

June 6th, 2019 - By Kevin Fogarty

When a  company puts together a software/hardware design team, it's not a bad idea to make sure where the final responsibility lies.

Asking the right questions
“In China I had a long conversation with the hardware engineer about what we were trying to do, and it eventually became clear he was not the one calling the shots,” said Kurt Shuler, vice president of marketing at Arteris IP. “It was the software architect calling the shots, so we all got together and that let us move forward once I realized the chip was defined by the algorithm, not the other way around.

”But the software architect doesn’t always have a good feel for the hardware. “The other problem we had was that, often, a software architect won’t be that good at abstracting down to the transistor level, and the hardware architect may not be good at abstracting up to the software, so you have to kind of walk them through that,” said Shuler.

Insisting on tight integration and optimization of software with hardware also may be a good way to coordinate development, but it doesn’t always reflect realistic performance requirements. Shuler noted that one way to help customers think about the problem is, rather than asking the hardware architect what would happen if the chip didn’t live up to expectations, to ask what the impact on the device would be if they were to remove the chip and replace it with an off-the-shelf inference chip that would have been completely generic to the application.

For more information, please download the Arteris FlexNoC Interconnect IP data sheet; https://www.arteris.com/download-flexnoc-datasheet

Topics: SoC semiconductor engineering noc interconnect ML software architects

Arteris IP at Synopsys Users Group Silicon Valley 2019


Arteris IP at SNUG Silicon Valley 2019 

Location: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA  
Track: Artificial Intelligence - Wednesday, 20 March, 3:45 pm - 4:30 pm

Arteris IP is presenting this paper, "Using Machine Learning for Characterization of NoC Components"

Topics: NoC semiconductor FlexNoC Soft IP SoCs RTL noc interconnect ML PPA

Semiconductor Engineering: Using AI Data For Security

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments about the edge emerging as a particular security concern because some of the devices can kill you, covered in this Semiconductor Engineering article;

Using AI Data For Security

February 20th, 2019 - By Ann Steffora Mutschler

Pushing data processing to the edge has opened up new security risks, and lots of new opportunities. 

The edge and beyond
“It’s cars and robots and medical devices,” said Kurt Shuler, vice president of marketing at Arteris IP. “These things can kill you two ways. A cosmic ray can cause a bit to flip, and things go awry. The other way is that the AI may work as intended, but what it decides to do from its neural net application is the wrong thing. In that case, the safety of the intended function is bad.”

There’s even a new spec just for this: “ISO/PAS 21448:2019 Road vehicles — Safety of the intended functionality.” That captures how to analyze these AI powered systems going into cars, so they works as designed.

Security can impact all of these systems. “There’s a totally separate set of specs, and a totally separate set of Ph.D. geeks working on safety and on security,” said Shuler. “What’s disconcerting is that the effects of any of these things, especially from a functional safety standpoint and a security standpoint, can be the same. Whether a bit flips or an engineer flipped a bit, someone can get hurt. Yet these sets of experts don’t really talk to each other too much. This was addressed in the new ISO 26262 2018 specification that came out in December, which includes specific text to address this. It basically says you must coordinate with security guys, but unless security is somehow mandated to a certain level — like functional safety is in cars and trains and other verticals — nobody really cares. It’s like insurance. Nobody wants to pay for too much security.”

For more information about ISO 26262:2018 Part 11, please download this presentation "Fundamentals of ISO 26262 Part 11 for Semiconductors".

Topics: semiconductor automotive AI ISO PAS 21448 data centers noc interconnect ML AI SoC Designers ecosystem

Semiconductor Engineering: The Race To Multi-Domain SoCs

 Arteris IP's CEO looks at how automotive and AI are Altering chip design in this article in Semiconductor Engineering;

The Race To Multi-Domain SoCs

February 7th,  2019 - By Ed Sperling

K. Charles Janac, president and CEO of Arteris IP, sat
down with Semiconductor Engineering to discuss the impact of automotive and AI on chip design. What follows are excerpts of that conversation.

SE: What do you see as the biggest changes over the next 12 to 24 months?
Janac: There are segments of the semiconductor market that are shrinking, such as DTV and simple IoT. Others are going through an investment phase, including automotive, AI/machine learning and China. You really want to be focused on those segments. 

SE: So does IP that’s being developed today look radically different than it did five years ago?
Janac:
Yes, everything is getting amazingly complex. What people are building right now are multi-domain SoCs. The CPU, which used to do all the work, does relatively less work. There are accelerators for vision and data analysis outside of the CPU subsystem. There are machine learning sections, some general-purpose, some very specific, all on-chip. There is a memory subsystem with very high-bandwidth memory and low latency. There also is functional safety. You need tremendous performance because a car is a supercomputer on wheels. The car has to be very efficient, because you need to deliver that compute power without water cooling. Power management becomes very sophisticated. And then there are functional safety and security subsystems to keep these safe from environmental and man-made issues.

SE: Where does the network on chip (NoC) fit into all of this?
Janac: All data goes through the NoC of the chip. There are opportunities for generating value from that. But the increase in complexity is increasing the number and sophistication of the interconnect parts of the chip. Before, you may have had networks on chip. Now you may have 20 or 30.

Topics: semiconductor automotive ADAS neural networks AI LIDAR flexnoc ai package noc interconnect ML AI SoC Designers chiplets