Arteris Articles

All About Circuits: The Role of Last-Level Cache Implementation for SoC Developers

Kurt Shuler, vice president of marketing at Arteris IP authored this new All About Circuits article:

The Role of Last-Level Cache Implementation for SoC Developers

May 13th, 2020 - By Kurt Shuler

There is a challenge for SoC developers to find ways to navigate the demand of memory in their design. This article looks at how a fourth, or last-level, cache can provide a solution.

So, what’s the best memory solution? For hints, we can look at what other companies are doing. Tear-down analyses have shown that Apple, for one, solves the speed mismatch problem by adding another cache. If a big company with nearly infinite R&D resources designs around its SoCs bottlenecks this way, it’s probably worth looking into. 
 
Topics: Apple SoC NoC technology CodaCache last level cache kurt shuler noc interconnect ML IP market security All About Circuits DSP

Arteris IP Awarded "Best Ecosystem Partner of 2019" by AI Pioneer Canaan

Last month, Canaan Inc. successfully went public with an IPO on Nasdaq. And just last week, our Arteris IP team was invited to attend a grand dinner to celebrate this wonderful achievement. During the dinner, Arteris IP was awarded by Canaan the "Best Ecosystem Partner of 2019 Award" which Rick Sun, our China Sales Manager (second from the right in the above photo) is holding. 

The entire Arteris IP team is proud that our efforts have helped contribute to Canaan's success on their AI chip, and we we look forward to more activities with them as they continue their explosive growth. This award is a testament not only to our products and technologies, but also the excellent Arteris IP team members supporting our customers worldwide.

Topics: semiconductor machine learning artificial intelligence AI SoCs flexnoc ai package noc interconnect ML

New! Arteris IP Technical Paper, Re-Architecting SoCs for the AI Era

Kurt Shuler, VP of Marketing at Arteris IP has written this 10-page technical paper titled, "Re-Architecting SoCs for the AI Era".

August 29, 2019 - by Kurt Shuler

Abstract:
The growth of artificial intelligence (AI) demands that semiconductor companies re-architect their system on chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data centers, AI applications require a rethink of memory structures, the numbers and types of heterogeneous processors and hardware accelerators, and careful consideration of how the dataflow is enabled and managed between the various high-performance IP blocks.

Topics: functional safety ISO 26262 semiconductor machine learning autonomous driving artificial intelligence AI SoCs kurt shuler noc interconnect ML dataflow

EE Times article, The Gatekeeper of a Successful Design is the Interconnect

K. Charles Janac, President and CEO, at Arteris IP, authored this article on how an effective interconnect makes delivering a complex SoC easier, more predictable, and less costly.

August 25, 2019 - by K. Charles Janac

An interconnect handles various types of traffic inside an SoC and is a mechanism for effective IP block integration. The interconnect is the most configurable IP in the SoC — typically changing many times during a project and nearly always changing between projects. It also plays a vital role in security and functional safety because it carries most of the SoC data and contains nearly all the SoC’s long wires and system-level services, including quality of service (QoS), visibility, physical awareness, and power management. The interconnect enables cache coherency in multiprocessor SoCs, high-performance and bandwidth levels in advanced driver assistance systems (ADAS) automotive chips and networking SoCs, and ultra-low power in long-running consumer devices.

Topics: semiconductor eetimes advanced driver assistance systems adas autonomous driving AI K. Charles Janac SoCs noc interconnect ML data center automation