Arteris Articles

SemiWiki: A Last-Level Cache for SoCs

JP Loison, Senior Corporate Application Architect at Arteris IP, chats with Bernard Murphy in this SemiWiki blog:

A Last-Level Cache for SoCs  

July 19th,  2018 - By Bernard Murphy

Based on a discussion with JP Loison, Bernard Murphy (SemiWiki) describes Arteris IP’s latest IP introduction - a last-level cache (LLC) for use outside the coherent domain, for accelerators and other IP that can benefit from cache support. He also touches on benefits offered by significant flexibility in adapting the IP for different use-models.

Topics: SoC cache coherent IP CPU Ncore semiwiki cache CodaCache on-chip memory performance multi-processor systems congestion configurability last level cache scratchpad way partitioning

New EE Times article on Automotive SoCs and Interconnect IP

EE Times just published a new article I wrote about how the automotive industry has replaced the mobile phone industry as the driver for new semiconductor technologies.

Read now: "Mission Critical in Auto SoC: Interconnect IP"

 

Topics: Arteris FlexNoC Ncore eetimes cache coherent interconnect

Arteris Ncore Cache Coherent Interconnect IP Featured in Linley Group Paper

Arteris' Ncore Cache Coherent Interconnect IP was featured in a Linley Group white paper titled, "Easing Heterogeneous Cache Coherent SoC Design using Arteris’ Ncore Interconnect."

Topics: white paper download Ncore cache coherent interconnect The Linley Group

Arteris Ncore cache coherent interconnect featured in Microprocessor Report (MPR)

Arteris' new Ncore Cache Coherent Interconnect IP was featured in a Microprocessor Report article. If you already subscribe to MPR, then you can go to this link to read it: http://www.linleygroup.com/mpr/article.php?id=11615

Topics: new product Ncore heterogeneous cache coherency The Linley Group