Arteris Articles

Semiconductor Engineering: Chiplets, Faster Interconnects, More Efficiency

 Arteris IP's K. Charles Janac, president and CEO, chats with Ed Sperling at Hot Chips in this latest Semiconductor Engineering article:

Chiplets, Faster Interconnects, More Efficiency

August 22nd, 2019 - By Ed Sperling

Big chipmakers are turning to architectural improvements such as chipsets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency.

 

“Everyone is struggling with CCIX,” said K. Charles Janac, president and CEO of Arteris IP. “If you have an accelerator and two coherent dies, there are too many corner cases to get it to work easily. But now you can use 3D interconnects to hook together a planar CPU and a planar I/O. So this looks like one system to the software, and you have inter-chip links between the network on chip and different die. That way you can support non-coherent and coherent read/write across two die. It makes the interconnect more valuable, but it also makes it more complicated.”

“The memory controller and the NoC will have to be much more tightly integrated,” said Janac. “The problem is that neither one understands the QoS of the entire chip, and there aren’t any independent memory controller companies left. But memory traffic has to be better integrated to make this work.”

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Topics: SoC ArterisIP FlexNoC ncore cache coherent interconnect semiconductor engineering K. Charles Janac noc interconnect Hot Chips