Arteris Articles

SemiWiki: On-Chip Networks at the Bleeding Edge of ML

On-chip networks become a lot more challenging at the high-end of machine learning (ML). Bernard Murphy (SemiWiki) talked with Kurt Shuler, VP Marketing at Arteris IP, about the experience they have developed over the years of working with well-known ML product builders and how this has influenced  the AI package recently released by Arteris IP in this SemiWiki blog:

On-Chip Networks at the Bleeding Edge of ML 

November 29th,  2018 - By Bernard Murphy

I wrote a while back about some of the more exotic architectures for machine learning (ML), especially for neural net (NN) training in the data center but also in some edge applications. In less hairy applications, we’re used to seeing CPU-based NNs at the low end, GPUs most commonly (and most widely known) in data centers as the workhorse for training, and for the early incarnations of some mobile apps (mobile AR/MR for example), FPGAs in applications where architecture/performance becomes more important but power isn’t super-constrained, DSPs in applications pushing performance per watt harder and custom designs such as the Google TPU pushing even harder.

Topics: SoC semiwiki kurt shuler NoC semiconductor machine learning FPGAs AI chips FlexNoC flexnoc ai package

SemiWiki: Supporting ASIL-D Through Your Network on Chip

Kurt Shuler, VP Marketing at Arteris IP has written a White-Paper 'How to efficiently achieve ASIL-D compliance using NoC technology', and discusses the details with Bernard Murphy in this SemiWiki blog:

Supporting ASIL-D Through Your Network on Chip 

September 20th,  2018 - By Bernard Murphy

ASIL-D compliance for safety (the top-level of safety)  in automotive applications has become much more prominent as a requirement than we might have expected. Bernard Murphy (SemiWiki) provides his take after reading Kurt Shuler’s white-paper on how the NoC interconnect connecting IPs can help meet this goal and why this approach to safety in integration is more efficient than some frequently discussed alternatives.

Topics: SoC semiwiki kurt shuler safety culture ISO 26262 ASIL D NoC compliance semiconductor ISO 26262 certification ASIL-B failure mitigation FMEDA

Semiconductor Engineering: Adding NoCs To FPGA SoC

Ty Garibay, CTO at Arteris IP, comments on Bridging the gap:

Adding NoCs To FPGA SoCs 


June 28th,  2018 - By Ann Steffora Mutschuler

As complexity and device sizes rise, so does the need for an on-chip network.

Topics: FlexNoC hardware functional safety FPGA SoCs arteris ip digital SerDes 100-gigabit HBM2 Ty Garibay CTO NoC

Asymmetric Multiprocessing with Heterogeneous Architectures: Use the Best Core for the Job

Often, the term “multiprocessing” is associated with tightly-coupled symmetric multiprocessing (SMP) architectures, due in large part to SMP’s prevalence in high-performance computing, x86/x64 servers, and PCs. Unfortunately, SMP’s incremental performance scaling for most applications decreases significantly with increasing numbers of cores. This lack of scalability has prompted many processor companies to avoid purely SMP solutions for their mobile and consumer electronics applications. Instead, they have implemented asymmetric multiprocessing (AMP) architectures to make more efficient use of silicon.

Topics: NoC Systems-on-Chip AMP symmetric multiprocessing HSA foundation on-chip interconnect OS