Arteris Articles

Semiconductor Engineering: Variables Complicate Safety-Critical Device Verification

Kurt Shuler, Vice President of Marketing at Arteris IP participates in this new "Experts at the Table" article in Semiconductor Engineering:

Variables Complicate Safety-Critical Device Verification 

July 1st, 2020 - By Ann Steffora Mutschler

What's the best way to approach designs like AI chips for automotive that can stand the test of time? 

 
SE: Where does the industry stand with the task of verifying safety-critical devices today?
 
Kurt Shuler responds, "At the chip level we still have a situation where the verification people and methodologies are separate from the functional safety people and methodologies. This results in some overlap and rework. As tools and data interchange standards (like IEEE P2851 being led by both IEEE and Accellera) mature, we’ll be able to have more automation where functional safety validation through fault injection can be executed as part of regular verification processes. This will help everyone in the industry have more confidence that products don’t regress in diagnostic coverage as new versions are developed and will provide integrators/users of safety-critical systems to more easily perform fault injection validation of safety mechanisms if they desire."
 
Topics: SoC ISO 26262 automotive NoC technology semiconductor engineering ASIL D AI chips noc interconnect IP market IEEE P2851 fault injection

SemiWiki: Where's the Value in Next-Gen Cars?

Bernard Murphy learns more from Kurt Shuler on the shifting landscape in the automotive electronics value chain in this new SemiWiki blog:

Where's the Value in Next-Gen Cars?

June 22th, 2020 - By Bernard Murphy

Value chains can be very robust and seemingly unbreakable – until they’re not. One we’ve taken for granted for many years is the chain for electronics systems in cars. The auto OEM, e.g. Toyota, gets electronics module from a Tier-1 supplier such as Denso. They, in turn, build their modules using chips from a semiconductor chip maker such as Renesas, who produces their chips using pre-packaged functions from IP providers like Arm. Toyota could do the whole thing themselves, but it’s very expensive to set-up and maintain all of that infrastructure. Specialization makes it all more practical. Everyone makes money doing their bit well and cost-effectively and being able to sell to multiple customers (Toyota, GM, BMW, etc.). However, that cash flow can be upended when disruptive innovations are thrown into the supply chain, in this case, a lot more intelligence and autonomy. I talked to Kurt Shuler (VP Marketing at Arteris IP) to get his view. Kurt is an IP supplier and has a unique viewpoint because he works with semis, Tier-1s and OEMs, with standard designs as well as newer AI-based designs. He’s also an active member of the ISO 26262 committee.

 

 

Topics: SoC ISO 26262 semiconductor Ncore mobileye FlexNoC autonomous driving AI semiwiki kurt shuler noc interconnect Tier 1s value-chain

Semiconductor Engineering: Interconnect Challenges Grow, Tools Lag

Benoit de Lescure, CTO at Arteris IP comments in this new Semiconductor Engineering article:

Interconnect Challenges Grow, Tools Lag 

June 15th, 2020 - By Brian Bailey

More data, smaller devices are hitting the limits of current technology. The fix may be expensive. 
 
Chips are growing. “Ten years ago, the interconnect would be concerned with about 10K gates,” says Benoit de Lescure, CTO for Arteris IP. “Now they need to interconnect 10M gates on a chip, so there’s been a very significant increase in complexity. The number of clients on the interconnect has increased.”
 
Topics: SoC NoC technology semiconductor engineering Benoit de Lescure CTO broadcast noc interconnect ai accelerators IP market networking chips multicast

Semiconductor Engineering: Aging Problems at 5nm and Below

Kurt Shuler, vice president of marketing at Arteris IP comments in this new Semiconductor Engineering article:

Aging Problems at 5 nm and Below 

June 11th, 2020 - By Brian Bailey

Semiconductor aging has moved from being a foundry issue to a user problem. As we get to 5nm and below, vectorless methodologies become too inaccurate. 
 
“The problem is that if somebody is doing their own chip, their own software in their own device, they have all the information they need to know, down to the transistor level, what that duty cycle is,” says Kurt Shuler, vice president of marketing at  Arteris IP . “But if you are creating a chip that other people will create software for, or if you’re providing a whole SDK and they’re modifying it, then you don’t really know. Those chip vendors have to provide to their customers some means to do that analysis.”
 
Topics: SoC automotive NoC technology semiconductor engineering kurt shuler noc interconnect IP market canary cells AI algorithms