Arteris Articles

Semiconductor Engineering: Chiplet Momentum Builds, Despite Tradeoffs

 Arteris IP's Kurt Shuler, Vice President of Marketing, contributes to this latest article in Semiconductor Engineering.

Topics: SoC semiconductor engineering kurt shuler noc interconnect IP design

Semiconductor Engineering: Interconnect Prominence In Fail-Operational Architectures

 Arteris IP's Kurt Shuler, Vice President of Marketing, authored this latest article in Semiconductor Engineering about moving toward "Fail Operational"

Topics: SoC automotive ADAS semiconductor engineering kurt shuler ISO PAS 21448 noc interconnect

Semiconductor Engineering: Make Your Own Energy

 Arteris IP's Kurt Shuler, Vice President of Marketing, quoted in the latest Semiconductor Engineering article.

Make Your Own Energy

May 2nd, 2019 - By Ann Steffora Mutschler

Efficient use of power and energy in electric vehicles and smart buildings will require innovative thinking. 

Where it works
Energy harvesting has been important to automotive systems, but not necessarily at the SoC level, said Kurt Shuler, vice president of marketing at Arteris IP. “In EV and hybrid automotive systems, regenerative braking is common and there’s efforts to harvest vibrational energy using piezoelectric transducer MEMS, but this technology will take a while to become mainstream.”

At the SoC level, the first place Arteris IP saw energy harvesting implemented was in 2014 with TI’s SimpleLink CC26xx energy-sipping IoT chips, which are designed to be powered by a separate MEMS-based power source. Even though these chips are relatively simple SoCs from a processing viewpoint, Shuler stressed that they are hugely complex from a power management standpoint. There are more than 20 different power and voltage domains along with dynamic voltage frequency scaling.

For more information, please download the Arteris FlexNoC Interconnect IP data sheet; https://www.arteris.com/download-flexnoc-datasheet

Topics: SoC automotive semiconductor engineering noc interconnect automotive systems EV hybrid

SemiWiki: ML and Memories: A Complex Relationship

Kurt Shuler, VP Marketing at Arteris IP, helped Bernard Murphy (SemiWiki) learn the multiple ways that different types of memory need to connect to these accelerators in the latest SemiWiki blog:

ML and Memories: A Complex Relationship

March 13th, 2019 - By Bernard Murphy

How do AI architectures connect with memories? The answer is more complex than in conventional SoC architectures.

No, I’m not going to talk about in in-memory-compute architectures. There’s interesting work being done there but here I’m going to talk here about mainstream architectures for memory support in Machine Learning (ML) designs. These are still based on conventional memory components/IP such as cache, register files, SRAM and various flavors of off-chip memory, including not yet “conventional” high-bandwidth memory (HBM). However, the way these memories are organized, connected and located can vary quite significantly between ML applications.

For more information, please visit the Arteris IP AI package webpage: http://www.arteris.com/flexnoc-ai-package

Topics: semiconductor artificial intelligence semiwiki kurt shuler flexnoc ai package noc interconnect cache coherence