Arteris Articles

Semiconductor Engineering: AI, Performance, Power, Safety Shine Spotlight on Last-Level Cache

Kurt Shuler, vice president of marketing at Arteris IP writes about overcoming memory limitations in automotive systems in this Semiconductor Engineering article:

AI, Performance, Power, Safety Shine Spotlight on Last-Level Cache

April 2nd, 2020 - By Kurt Shuler

Memory limitations to performance, always important in modern systems, have become an especially significant concern in automotive safety-critical applications making use of AI methods. On one hand, detecting and reporting a potential collision or other safety problem has to be very fast. Any corrective action is constrained by physics and has to be taken well in advance to avoid the problem.
 
Topics: SoC automotive NoC technology semiconductor engineering CodaCache performance last level cache noc interconnect IP market

Arteris IP at DVCon 2019 Silicon Valley

Arteris IP at DVCon U.S. 2019 

Location: DoubleTree Hotel, 2050 Gateway Place, San Jose, CA
Poster Sessions: Tuesday, 26 February, 10:30am - 12:00pm, Gateway Foyer, 2nd level

Arteris IP is presenting the poster, "4.8 Flex-Checker: A One Stop Shop for all your Checkers: A Methodology for Elastic Score-boarding"

Topics: NoC hardware verification semiconductor latency bandwidth SoCs performance noc interconnect

SemiWiki: A Last-Level Cache for SoCs

JP Loison, Senior Corporate Application Architect at Arteris IP, chats with Bernard Murphy in this SemiWiki blog:

A Last-Level Cache for SoCs  

July 19th,  2018 - By Bernard Murphy

Based on a discussion with JP Loison, Bernard Murphy (SemiWiki) describes Arteris IP’s latest IP introduction - a last-level cache (LLC) for use outside the coherent domain, for accelerators and other IP that can benefit from cache support. He also touches on benefits offered by significant flexibility in adapting the IP for different use-models.

Topics: SoC cache coherent IP CPU Ncore semiwiki cache CodaCache on-chip memory performance multi-processor systems congestion configurability last level cache scratchpad way partitioning