Arteris Articles

Arteris IP at DVCon 2019 Silicon Valley

Arteris IP at DVCon U.S. 2019 

Location: DoubleTree Hotel, 2050 Gateway Place, San Jose, CA
Poster Sessions: Tuesday, 26 February, 10:30am - 12:00pm, Gateway Foyer, 2nd level

Arteris IP is presenting the poster, "4.8 Flex-Checker: A One Stop Shop for all your Checkers: A Methodology for Elastic Score-boarding"

Topics: NoC semiconductor noc interconnect SoCs bandwidth latency performance hardware verification

SemiWiki: A Last-Level Cache for SoCs

JP Loison, Senior Corporate Application Architect at Arteris IP, chats with Bernard Murphy in this SemiWiki blog:

A Last-Level Cache for SoCs  

July 19th,  2018 - By Bernard Murphy

Based on a discussion with JP Loison, Bernard Murphy (SemiWiki) describes Arteris IP’s latest IP introduction - a last-level cache (LLC) for use outside the coherent domain, for accelerators and other IP that can benefit from cache support. He also touches on benefits offered by significant flexibility in adapting the IP for different use-models.

Topics: SoC semiwiki CodaCache cache on-chip memory CPU performance multi-processor systems Ncore cache coherent IP last level cache scratchpad way partitioning congestion configurability