Arteris Articles

Arteris IP is Hiring a Hardware Verification Engineer in Paris!

Featured Position!

Hardware Verification Engineer in Paris (Guyancourt), France

Do you want to contribute to the backbone of the some of the world's most popular SoCs? You will work with an expert team to design and deliver interconnect & memory hierarchy solutions. You'll verify designs created in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll have to ensure that our IPs are matching the specifications before been released to our customers, to be part of a SoC for AI, IoT, automotive, mobile... our IP is used everywhere!

Topics: hardware verification arteris ip RTL noc interconnect job SoC designs C/C++ Python

Arteris IP is Hiring a Senior Hardware Verification Engineer in Austin, TX!

Featured Position!

Senior Hardware Verification Engineer
for our Austin, TX Office

Do you want to contribute to the backbone of the some of the world's most popular SoCs?

You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll go home at the end of the day amazed at all the places where your creations end up. 

Topics: arteris ip hardware RTL noc interconnect job SoC designs Verilog

Semiconductor Engineering: How To Build An Automotive Chip

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments about the claims of technical safety requirements in this Semiconductor Engineering article;

How To Build An Automotive Chip

March 7th, 2019 - By Ann Steffora Mutschler

Changing standards, stringent requirements and a mix of expertise make this a tough marketing to crack.

IP issues
“One of the things that all of these guys deal with is having evidence that the specifications are being followed, both from a process standpoint of how the IP is designed,” said Kurt Shuler, vice president of marketing at Arteris IP. “And then, does the IP meet the technical safety requirements that are being claimed?”

This requires the IP customer to look closely at their different IP providers. “If I’m licensing some IP, I want to understand in pre-sales what do you have, how did you build it,” said Shuler. “What evidence and work products do you have to prove any claims that you make? Things may go quiet for a while until the design team gets closer to the end of the chip design project and starts doing the work where they have to calculate the diagnostic coverage and FMEDA, maybe some fault injection to validate, some of the assumptions they make in the FMEDA, among other activities.”

“If our customer or prospect has somebody who doesn’t understand functional safety or the specification, and is just going blindly through a checklist, it slows things down,” Shuler said. “So the right subject matter experts must be there.”

For more information about ISO 26262:2018 Part 11, please download this presentation "Fundamentals of ISO 26262 Part 11 for Semiconductors".

Topics: SoC functional safety ISO 26262 automotive semiconductor engineering AI RTL noc interconnect ML/AI

Arteris IP at Synopsys Users Group Silicon Valley 2019


Arteris IP at SNUG Silicon Valley 2019 

Location: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA  
Track: Artificial Intelligence - Wednesday, 20 March, 3:45 pm - 4:30 pm

Arteris IP is presenting this paper, "Using Machine Learning for Characterization of NoC Components"

Topics: NoC semiconductor FlexNoC Soft IP SoCs RTL noc interconnect ML PPA