Arteris Articles

Semiconductor Engineering: Racing To The Edge

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments in the latest Semiconductor Engineering article.

Racing To The Edge

April 9th, 2019 - By Susan Rambo and Ed Sperling

The race is on to win a piece of the edge despite the fact that there is no consistent definition of where the edge begins and ends or how the various pieces will be integrated or ultimately tested.

Safety lives at the edge
“The edge includes a lot of the stuff where people are most concerned about things that can kill you, like cars and robots and medical devices,” said Kurt Shuler, vice president of Arteris IP. “These things can kill you two ways. One is a cosmic ray and the traditional functional safety use case, where it flips a bit and then it goes awry. The other way is everything works as intended, however what it does and what it decides to do from its neural net application is the wrong thing. There’s not a cosmic ray. There’s not a hardware safety problem. The safety of the intended function is bad. (There is a new specification out for that, ISO/PAS 21448:2019 Road Vehicles — Safety of the Intended Functionality.)”

For more information on AI, please click on the Arteris FlexNoC AI Package webpage: http://www.arteris.com/flexnoc-ai-package.

Topics: SoC ARM automotive semiconductor engineering safety noc interconnect edge ISO/PAS Intended functionality

Semiconductor Engineering: Regulations Trail Autonomous Vehicles

Ty Garibay, CTO at Arteris IP, shares his insight in this Semiconductor Engineering article:

Regulations Trail Autonomous Vehicles

 

July 9th, 2018 - By Kevin Fogarty

Topics: SoC semiconductor autonomous vehicles autonomous driving semiconductor engineering arteris ip safety

Design & Reuse: Interconnect for AI and Automotive Solutions Video

Kurt Shuler, VP of Marketing at Arteris IP, discusses AI and Automotive in this video:

Design & Reuse: Arteris IP Interconnect for AI and Automotive Solutions 

June 26th, 2018 

Gabrielle interviews Kurt Shuler at DAC 2018, San Francisco, CA

Topics: ADAS autonomous vehicles ISO 26262 training FlexNoC ISO 26262 compliance ISO 26262 certification ISO 26262 specification ASIL D safety functional safety manager

Semiconductor Engineering: 7nm Design Challenges Video

Tech Talk: Why the next nodes will be so expensive, and how they will play out in chip design.

Tech Talk Video: 7nm Design Challenges 

July 9th,  2018 - By Ed Sperling

Ed Sperling interviews Ty Garibay, CTO at Arteris IP headquarters about the challenges of moving to 7nm, who’s likely to head there, how long it will take to develop chips at that node, and why it will be so expensive. This also raises questions about whether chips will begin to disaggregate at 7nm and 5nm.

Topics: FlexNoC safety tech talk video 7nm