Arteris Articles

SemiWiki: How Should I Cache Thee? Let Me Count the Ways

Kurt Shuler, VP Marketing at Arteris IP, updates Bernard Murphy (SemiWiki), on some of the interesting ways AI is driving caching in this new SemiWiki blog:

How Should I Cache Thee? Let Me Count the Ways

September 25th, 2019 - By Bernard Murphy

Caching is well-known as a method to increase processing performance and reduce power by reducing need for repeated accesses to main memory. What may be less well-known is how varied this technique has become, especially in and around AI accelerators. 

Caching intent largely hasn’t changed since we started using the concept – to reduce average latency in memory accesses and to reduce average power consumption in off-chip reads and writes. The architecture started out simple enough, a small memory close to a processor, holding most-recently accessed instructions and data at some level of granularity (e.g. a page). Caching is a statistical bet; typical locality of reference in the program and data will ensure that multiple reads and writes can be made very quickly to that nearby cache memory before a reference is made outside that range. When a reference is out-of-range, the cache must be updated by a slower access to off-chip main memory. On average a program runs faster because, on average, the locality of reference bet pays off.

You can learn more by visiting the Arteris IP Ncore Cache Coherent Interconnect IP webpage; and the CodaCache Last Level Cache IP webpage;

Topics: SoC semiconductor automotive artificial intelligence ncore cache coherent interconnect semiwiki CodaCache kurt shuler noc interconnect ai accelerators

EE Times article, The Age of the Monster Chip

K. Charles Janac, President and CEO, at Arteris IP, authored this article on what is now defined as a "Monster Chip".

September 19, 2019 - by K. Charles Janac

What are the system designs that require a leap in SoC complexity? It’s not only big datacenter artificial intelligence (AI) chips, but also autonomous vehicles such as cars, trucks and drones; they are self-landing, reusable rockets; they are medical devices carrying out remote diagnostics; and they are connected machine tool controllers supporting smart manufacturing.

These chips are starting to be referred to as “Monster Chips” because of both the size and complexity.

Topics: semiconductor ADAS eetimes autonomous driving AI K. Charles Janac SoCs noc interconnect data center automation blockchain big chips

SemiWiki: AI, Safety and the Network

Kurt Shuler, VP Marketing at Arteris IP, and Bernard Murphy (SemiWiki) discuss, 'What is driving the boom in AI-centric design', in this new SemiWiki blog:

AI, Safety and the Network

September 4th, 2019 - By Bernard Murphy

You probably know that Arteris IP is very active in AI and safety, leveraging their central value in network-on-chip (NoC) architectures. Bernard Murphy of SemiWiki blogged on Kurt Shuler's front-to-back white-paper to walking us through the essentials of AI, particularly machine learning (ML) and its application for example in cars.

Kurt also highlights an interesting point about this rapidly evolving technology. As we build automation from the edge to the fog to the cloud, functionality, including AI, remains quite fluid between levels. Kurt points out that this is somewhat mirrored in SoC design. In both cases architecture is constrained by need to optimize performance and minimize power across the system through intelligent bandwidth allocation and data locality. And for safety-critical applications, design and verification for safety around intelligent features must be checked not only within and between SoCs in the car but also beyond, for example in V2x communication between cars and other traffic infrastructure.

You can learn more by downloading this Arteris IP white paper titled, Re-Architecting SoCs for the AI Era:

Topics: SoC functional safety ISO 26262 semiconductor automotive ADAS machine learning artificial intelligence semiwiki kurt shuler flexnoc ai package noc interconnect

New! Arteris IP Technical Paper, Re-Architecting SoCs for the AI Era

Kurt Shuler, VP of Marketing at Arteris IP has written this 10-page technical paper titled, "Re-Architecting SoCs for the AI Era".

August 29, 2019 - by Kurt Shuler

The growth of artificial intelligence (AI) demands that semiconductor companies re-architect their system on chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data centers, AI applications require a rethink of memory structures, the numbers and types of heterogeneous processors and hardware accelerators, and careful consideration of how the dataflow is enabled and managed between the various high-performance IP blocks.

Topics: functional safety ISO 26262 semiconductor machine learning autonomous driving artificial intelligence AI SoCs kurt shuler noc interconnect ML dataflow