Arteris Articles

Semiconductor Engineering: In-System Networks Are Front And Center

 Arteris IP's Kurt Shuler, VP of Marketing, authored this article and offers his perspective on HotChips 2019 in this latest Semiconductor Engineering:

In-System Networks Are Front And Center

September 15th, 2019 - By Kurt Shuler

AI demands push innovation in design architectures and techniques.

 

This year’s HotChips conference at Stanford was all about artificial intelligence (AI) and machine learning (ML) and what particularly struck me, naturally because we’re in this business too, was how big a role on-chip networks played in some of the leading talks.

Giant leaps are being made in supporting new AI architectures, tuning them for optimum performance per milliwatt and embedding them effectively into traditional and novel SoC architectures.

You can learn more by reading my white paper titled, "Re-Architecting SoCs for the AI Era". Download is free; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era

Topics: SoC functional safety ISO 26262 machine learning cache coherency semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448 Hot Chips bigger chips

Semiconductor Engineering: Autonomous Vehicles Are Reshaping The Tech World

 Arteris IP's Kurt Shuler, VP of Marketing, comments on ISO 26262 and the need to add SOTIF for the unknown-unkown errors in this latest Semiconductor Engineering article:

Autonomous Vehicles Are Reshaping The Tech World

September 5th, 2019 - By Kevin Fogarty

Even before fully autonomous vehicles blanket the road there is major upheaval at all levels of the industry.

 

Until recently, the V-system testing of ISO 26262 has been the primary functional safety method for verification and validation. It will continue to play that role, according to Kurt Shuler, vice president of marketing at Arteris IP, but it will be supplemented by other types of testing such as SOTIF (safety of the intended functionality, ISO 21448).

“SOTIF was a little controversial,” Shuler said. “It almost didn’t get passed because of what I call the philosophical element. It is designed to find faults when things are working correctly, but it also finds errors that you don’t know about. The way it goes about that is a little different from the usual approach, but there are also standards coming from SAE and others from ISO, so there will be plenty of competition for this kind of challenge to be able to verify probabilistic systems.”

For more information, please visit our Resources page for free downloads of our technical papers; http://www.arteris.com/resources

Topics: SoC ISO 26262 autonomous driving ArterisIP FlexNoC semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448

Semiconductor Engineering: Chiplets, Faster Interconnects, More Efficiency

 Arteris IP's K. Charles Janac, president and CEO, chats with Ed Sperling at Hot Chips in this latest Semiconductor Engineering article:

Chiplets, Faster Interconnects, More Efficiency

August 22nd, 2019 - By Ed Sperling

Big chipmakers are turning to architectural improvements such as chipsets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency.

 

“Everyone is struggling with CCIX,” said K. Charles Janac, president and CEO of Arteris IP. “If you have an accelerator and two coherent dies, there are too many corner cases to get it to work easily. But now you can use 3D interconnects to hook together a planar CPU and a planar I/O. So this looks like one system to the software, and you have inter-chip links between the network on chip and different die. That way you can support non-coherent and coherent read/write across two die. It makes the interconnect more valuable, but it also makes it more complicated.”

“The memory controller and the NoC will have to be much more tightly integrated,” said Janac. “The problem is that neither one understands the QoS of the entire chip, and there aren’t any independent memory controller companies left. But memory traffic has to be better integrated to make this work.”

For more information, please visit our Resources page for free downloads of our technical papers; http://www.arteris.com/resources

Topics: SoC ArterisIP FlexNoC ncore cache coherent interconnect semiconductor engineering K. Charles Janac noc interconnect Hot Chips

Semiconductor Engineering: Where Should Auto Sensor Data Be Processed?

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments in this latest Semiconductor Engineering article:

Where Should Auto Sensor Data Be Processed?

August 1st, 2019 - By Ann Steffora Mutschler

Fully autonomous vehicles are coming, but not as quickly as the initial hype would suggest...

 

Indeed, when it comes to processing the sensor data, a number of approaches currently point to allowing for scaling between different ADAS levels, but which the best way to do that is still up for debate.

“There must be an architecture they can do that with, and the question is, ‘How do you do that?'” said Kurt Shuler, vice president of marketing at Arteris IP. “There’s a lot of interest in getting more hardware accelerators to manage the communications in software, and directly managing the memory. For this, cache coherence is growing in importance. But how do you scale a cache coherent system? This must be done in an organized way, as well as adding a whole bunch of masters and slaves to it, such as additional clusters.”

For more information, please download the Arteris FlexNoC Interconnect IP data sheet; https://www.arteris.com/download-flexnoc-datasheet

Topics: SoC autonomous driving ArterisIP FlexNoC semiconductor engineering LIDAR noc interconnect cache coherence hardware accelerators