Arteris Articles

Semiconductor Engineering: AI, Performance, Power, Safety Shine Spotlight on Last-Level Cache

Kurt Shuler, vice president of marketing at Arteris IP writes about overcoming memory limitations in automotive systems in this Semiconductor Engineering article:

AI, Performance, Power, Safety Shine Spotlight on Last-Level Cache

April 2nd, 2020 - By Kurt Shuler

Memory limitations to performance, always important in modern systems, have become an especially significant concern in automotive safety-critical applications making use of AI methods. On one hand, detecting and reporting a potential collision or other safety problem has to be very fast. Any corrective action is constrained by physics and has to be taken well in advance to avoid the problem.
 
Topics: SoC automotive NoC technology semiconductor engineering CodaCache performance last level cache noc interconnect IP market

Semiconductor Engineering: A Promising Future For Interconnect IP

Rich Wawrzyniak of Semico Research describes the market drivers for advanced multicore SoC architectures and the critical role of NoC interconnect semiconductor intellectual property (IP) in this Semiconductor Engineering article:

A Promising Future For Interconnect IP

March 18th, 2020 - By Rich Wawrzyniak

Complexity of SoC designs continues to 

increase primarily due to increased demand for functionality and performance in all electronic devices. Studies that Semico Research has conducted on the SoC design landscape shows the number of discrete SIP blocks has continued to rise in response to increased market requirements from new applications and richer feature sets.

Topics: SoC NoC technology semiconductor engineering AI chips noc interconnect IP market

Semiconductor Engineering: New Architectural Issues Facing Auto Ecosystem

Kurt Shuler, vice president of marketing at Arteris IP comments, technology-wise, there are two key trends - electrification and autonomy, then who owns the data in this new Semiconductor Engineering article:

New Architectural Issues Facing Auto Ecosystem

March 5th, 2020 - By Ann Steffora Mutschler

Semiconductor vendors are trying to do more system-level work, while EDA companies are starting to integrate some of their tools and IP, so they all work together, Shuler said. “For the Tier 1s this means, just like the hyperscalar companies like the Googles, the Facebooks, the Amazons, and the Microsofts, they are now designing their own chips. That means they’re competing below and they’re competing above. ‘Mr. OEM, we can take care of all of this for you. You just make the plastics. You don’t need to know how all this stuff works.’ And the OEMs are now saying, ‘Hey, wait a minute, this is our brand, this is our car. We need to start hiring chip people too.’ Everybody is, within the car itself, clashing from a business and technical standpoint,” Shuler said.

There are other potential conflicts and challenges to go along with this, such as what to do when data comes into a car, where and how that data should be processed, and who ultimately owns the data.

“Think about how much data your cell phone creates, as well as all of the security breaches that have happened,” said Arteris IP’s Shuler. “The car has a whole bunch of information just like that cell phone, and there’s a fight over who owns that info.

To learn more, please download this Technical Paper on "Re-Architecting SoCs for the AI Era", please go here; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era

Topics: SoC ISO 26262 Networks-On-Chip autonomous vehicles semiconductor engineering arteris ip kurt shuler OEMs noc interconnect ML/AI Tier 1s electrification

Semiconductor Engineering: Uses, Limits and Questions for FPGAs and Autos

Kurt Shuler, vice president of marketing at Arteris IP comments, he has seen that development is quickly moving in the direction of optimization with a lot of custom ASIC activity this Semiconductor Engineering article:

Uses, Limits and Questions for FPGAs and Autos

February 6th, 2020 - By Ann Steffora Mutschler

 

 

“Some companies are getting beyond the bounds of what can be done even in single die, looking at multidie solutions, but everything’s around optimization for power, bandwidth, latency, and functional safety,” Shuler said. “When you go to FPGA, the biggest issue is probably on the power side. Compared to a similar set of logic in ASIC versus doing an FPGA, you’ve got to basically turn on and off more transistors. That’s the underlying technical issue.

To learn more, please download this Technical Paper on "Re-Architecting SoCs for the AI Era", please go here; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era

Topics: SoC Networks-On-Chip ASICs autonomous vehicles semiconductor engineering arteris ip kurt shuler noc interconnect ML/AI sensors