Arteris Articles

Semiconductor Engineering: CEO Outlook: 2020 Vision

 Arteris IP's CEO, Charlie Janac, is quoted in a 2020 survey of CEOs from across the country in this Semiconductor Engineering article:

CEO Outlook: 2020 Vision

January 6th, 2020 - By Ed Sperling

5G, China and AI are prominent, but big changes are coming everywhere.

 

“In 2020, highway driving starts to become real for autonomous vehicles,” said K. Charles Janac, CEO of ArterisIP. “You’re also going to see more applications for machine learning and AI emerge. Right now, there is too much money being spent on this by big Internet companies that are doing a lot internally. Those investments will shift. You’ll also see 5G becoming very important. We will need that for the last mile. The other killer app is cyber security, and this is one that is somewhat worrisome because we’re starting to see 5G and machine learning being used to track entire populations.”

To learn more, please download this Technical Paper on "Re-Architecting SoCs for the AI Era", please go here; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era

Topics: SoC Networks-On-Chip autonomous vehicles semiconductor engineering arteris ip K. Charles Janac charlie janac noc interconnect ML/AI 5G cyber security

Semiconductor Engineering: Safety Islands In Safety-Critical Hardware

 Arteris IP's Kurt Shuler, vice president of marketing, authored this latest article in Semiconductor Engineering, from a joint Arm, Arteris IP and Dream Chip presentation at Arm TechCon 2019:

Safety Islands In Safety Critical Hardware

November 7th, 2019 - By Kurt Shuler

Creating a reliable place to manage critical functions when a design contains a mix of ASILs.

 

Safety and security have certain aspects in common so it shouldn’t be surprising that some ideas evolving in one domain find echoes in the other. In hardware design, a significant trend has been to push security-critical functions into a hardware root-of-trust (HRoT) core, following a philosophy of putting all (or most) of those functions in one basket and watching that basket very carefully. A somewhat similar principle applies for safety islands in safety-critical designs, in this case a core which will continue to function safely under all possible circumstances. The objective is the same – a reliable center for managing critical behavior, though from there the implementation details diverge.

For more information on this presentation and to download, please go here; https://www.arteris.com/download-arm-techcon-implementing-iso-26262-compliant-ai-systems-on-chip-with-arm-arteris

Topics: SoC economics ARM ISO 26262 ASIL D semiconductor engineering arteris ip kurt shuler noc interconnect Dream Chip

Semiconductor Engineering: Planning For Failures In Automotive

 Arteris IP's Kurt Shuler, VP of Marketing, comments on Bigger Chips in this latest Semiconductor Engineering:

Planning For Failures In Automotive

November 7th, 2019 - By Ann Steffora Mutschler

With more consolidation of functions within the ECUs in vehicles, the chips are getting bigger.

 In fact, they’re much larger and more sophisticated than
any chip in a cell phone, and have many more brains on it, noted Kurt Shuler, vice president of marketing at Arteris IP. “They’re more like something you would find in a data center, but it’s in your car. It’s got to sip power from a battery and it can’t have too much heat, so they’ve got all these different challenges. Then, if you look at the design teams that do this stuff, as design approaches change to anticipate failures, this is the reason why the traditional semiconductor companies are having trouble adapting — companies that have been incumbents and have done automotive chips for years.”

The ISO 26262 spec has been adapted to accommodate this in that fault injection can be done at a higher level than post synthesis, and can be run at the RTL functional level. “Still, getting some of the automotive guys to accept that this is acceptable is a challenge, but it’s progressing,” he added.

You can learn more by going to the Arteris IP Resources page and download presentations, technical papers, and view videos here; https://www.arteris.com/resources

Topics: SoC functional safety ISO 26262 semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448 bigger chips

Semiconductor Engineering: In-System Networks Are Front And Center

 Arteris IP's Kurt Shuler, VP of Marketing, authored this article and offers his perspective on HotChips 2019 in this latest Semiconductor Engineering:

In-System Networks Are Front And Center

September 15th, 2019 - By Kurt Shuler

AI demands push innovation in design architectures and techniques.

 

This year’s HotChips conference at Stanford was all about artificial intelligence (AI) and machine learning (ML) and what particularly struck me, naturally because we’re in this business too, was how big a role on-chip networks played in some of the leading talks.

Giant leaps are being made in supporting new AI architectures, tuning them for optimum performance per milliwatt and embedding them effectively into traditional and novel SoC architectures.

You can learn more by reading my white paper titled, "Re-Architecting SoCs for the AI Era". Download is free; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era

Topics: SoC functional safety ISO 26262 machine learning cache coherency semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448 Hot Chips bigger chips