Arteris Articles

Semiconductor Engineering: Safety Islands In Safety-Critical Hardware

 Arteris IP's Kurt Shuler, vice president of marketing, authored this latest article in Semiconductor Engineering, from a joint Arm, Arteris IP and Dream Chip presentation at Arm TechCon 2019:

Safety Islands In Safety Critical Hardware

November 7th, 2019 - By Kurt Shuler

Creating a reliable place to manage critical functions when a design contains a mix of ASILs.

 

Safety and security have certain aspects in common so it shouldn’t be surprising that some ideas evolving in one domain find echoes in the other. In hardware design, a significant trend has been to push security-critical functions into a hardware root-of-trust (HRoT) core, following a philosophy of putting all (or most) of those functions in one basket and watching that basket very carefully. A somewhat similar principle applies for safety islands in safety-critical designs, in this case a core which will continue to function safely under all possible circumstances. The objective is the same – a reliable center for managing critical behavior, though from there the implementation details diverge.

For more information on this presentation and to download, please go here; https://www.arteris.com/download-arm-techcon-implementing-iso-26262-compliant-ai-systems-on-chip-with-arm-arteris

Topics: SoC economics ARM ISO 26262 ASIL D semiconductor engineering arteris ip kurt shuler noc interconnect Dream Chip

Semiconductor Engineering: Planning For Failures In Automotive

 Arteris IP's Kurt Shuler, VP of Marketing, comments on Bigger Chips in this latest Semiconductor Engineering:

Planning For Failures In Automotive

November 7th, 2019 - By Ann Steffora Mutschler

With more consolidation of functions within the ECUs in vehicles, the chips are getting bigger.

 In fact, they’re much larger and more sophisticated than
any chip in a cell phone, and have many more brains on it, noted Kurt Shuler, vice president of marketing at Arteris IP. “They’re more like something you would find in a data center, but it’s in your car. It’s got to sip power from a battery and it can’t have too much heat, so they’ve got all these different challenges. Then, if you look at the design teams that do this stuff, as design approaches change to anticipate failures, this is the reason why the traditional semiconductor companies are having trouble adapting — companies that have been incumbents and have done automotive chips for years.”

The ISO 26262 spec has been adapted to accommodate this in that fault injection can be done at a higher level than post synthesis, and can be run at the RTL functional level. “Still, getting some of the automotive guys to accept that this is acceptable is a challenge, but it’s progressing,” he added.

You can learn more by going to the Arteris IP Resources page and download presentations, technical papers, and view videos here; https://www.arteris.com/resources

Topics: SoC functional safety ISO 26262 semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448 bigger chips

Semiconductor Engineering: In-System Networks Are Front And Center

 Arteris IP's Kurt Shuler, VP of Marketing, authored this article and offers his perspective on HotChips 2019 in this latest Semiconductor Engineering:

In-System Networks Are Front And Center

September 15th, 2019 - By Kurt Shuler

AI demands push innovation in design architectures and techniques.

 

This year’s HotChips conference at Stanford was all about artificial intelligence (AI) and machine learning (ML) and what particularly struck me, naturally because we’re in this business too, was how big a role on-chip networks played in some of the leading talks.

Giant leaps are being made in supporting new AI architectures, tuning them for optimum performance per milliwatt and embedding them effectively into traditional and novel SoC architectures.

You can learn more by reading my white paper titled, "Re-Architecting SoCs for the AI Era". Download is free; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era

Topics: SoC functional safety ISO 26262 machine learning cache coherency semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448 Hot Chips bigger chips

Semiconductor Engineering: Autonomous Vehicles Are Reshaping The Tech World

 Arteris IP's Kurt Shuler, VP of Marketing, comments on ISO 26262 and the need to add SOTIF for the unknown-unkown errors in this latest Semiconductor Engineering article:

Autonomous Vehicles Are Reshaping The Tech World

September 5th, 2019 - By Kevin Fogarty

Even before fully autonomous vehicles blanket the road there is major upheaval at all levels of the industry.

 

Until recently, the V-system testing of ISO 26262 has been the primary functional safety method for verification and validation. It will continue to play that role, according to Kurt Shuler, vice president of marketing at Arteris IP, but it will be supplemented by other types of testing such as SOTIF (safety of the intended functionality, ISO 21448).

“SOTIF was a little controversial,” Shuler said. “It almost didn’t get passed because of what I call the philosophical element. It is designed to find faults when things are working correctly, but it also finds errors that you don’t know about. The way it goes about that is a little different from the usual approach, but there are also standards coming from SAE and others from ISO, so there will be plenty of competition for this kind of challenge to be able to verify probabilistic systems.”

For more information, please visit our Resources page for free downloads of our technical papers; http://www.arteris.com/resources

Topics: SoC ISO 26262 autonomous driving ArterisIP FlexNoC semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448