Arteris Articles

Semiconductor Engineering: Machine Learning Drives High-Level Synthesis Boom

 Arteris IP's Kurt Shuler, Vice President of Marketing, quoted in the latest Semiconductor Engineering article:

Machine Learning Drives High-Level Synthesis Boom

June 6th, 2019 - By Kevin Fogarty

When a  company puts together a software/hardware design team, it's not a bad idea to make sure where the final responsibility lies.

Asking the right questions
“In China I had a long conversation with the hardware engineer about what we were trying to do, and it eventually became clear he was not the one calling the shots,” said Kurt Shuler, vice president of marketing at Arteris IP. “It was the software architect calling the shots, so we all got together and that let us move forward once I realized the chip was defined by the algorithm, not the other way around.

”But the software architect doesn’t always have a good feel for the hardware. “The other problem we had was that, often, a software architect won’t be that good at abstracting down to the transistor level, and the hardware architect may not be good at abstracting up to the software, so you have to kind of walk them through that,” said Shuler.

Insisting on tight integration and optimization of software with hardware also may be a good way to coordinate development, but it doesn’t always reflect realistic performance requirements. Shuler noted that one way to help customers think about the problem is, rather than asking the hardware architect what would happen if the chip didn’t live up to expectations, to ask what the impact on the device would be if they were to remove the chip and replace it with an off-the-shelf inference chip that would have been completely generic to the application.

For more information, please download the Arteris FlexNoC Interconnect IP data sheet; https://www.arteris.com/download-flexnoc-datasheet

Topics: SoC semiconductor engineering noc interconnect ML software architects

Semiconductor Engineering: Chiplet Momentum Builds, Despite Tradeoffs

 Arteris IP's Kurt Shuler, Vice President of Marketing, contributes to this latest article in Semiconductor Engineering.

Topics: SoC semiconductor engineering kurt shuler noc interconnect IP design

Semiconductor Engineering: Interconnect Prominence In Fail-Operational Architectures

 Arteris IP's Kurt Shuler, Vice President of Marketing, authored this latest article in Semiconductor Engineering about moving toward "Fail Operational"

Topics: SoC automotive ADAS semiconductor engineering kurt shuler ISO PAS 21448 noc interconnect

Semiconductor Engineering: Make Your Own Energy

 Arteris IP's Kurt Shuler, Vice President of Marketing, quoted in the latest Semiconductor Engineering article.

Make Your Own Energy

May 2nd, 2019 - By Ann Steffora Mutschler

Efficient use of power and energy in electric vehicles and smart buildings will require innovative thinking. 

Where it works
Energy harvesting has been important to automotive systems, but not necessarily at the SoC level, said Kurt Shuler, vice president of marketing at Arteris IP. “In EV and hybrid automotive systems, regenerative braking is common and there’s efforts to harvest vibrational energy using piezoelectric transducer MEMS, but this technology will take a while to become mainstream.”

At the SoC level, the first place Arteris IP saw energy harvesting implemented was in 2014 with TI’s SimpleLink CC26xx energy-sipping IoT chips, which are designed to be powered by a separate MEMS-based power source. Even though these chips are relatively simple SoCs from a processing viewpoint, Shuler stressed that they are hugely complex from a power management standpoint. There are more than 20 different power and voltage domains along with dynamic voltage frequency scaling.

For more information, please download the Arteris FlexNoC Interconnect IP data sheet; https://www.arteris.com/download-flexnoc-datasheet

Topics: SoC automotive semiconductor engineering noc interconnect automotive systems EV hybrid