Arteris Articles

Semiconductor Engineering: What Makes A Good Accelerator

Kurt Shuler, VP of Marketing at Arteris IP, comments on 'What needs to be accelerated' in this Semiconductor Engineering article:

What Makes A Good Accelerator

 

October 25th, 2018 - By Ann Steffora Mutschler

Topics: FPGAs machine learning neural network semiconductor engineering soc architecture arteris ip SoCs

Semiconductor Engineering: Not Enough Respect for SoC Interconnect

K. Charles Janac, CEO at Arteris IP, shares his opinion in this week's blog appearing in Semiconductor Engineering:

Not Enough Respect for SoC Interconnect

 

July 30th, 2018 - By K. Charles Janac

Topics: SoC functional safety SoC security semiconductor advanced driver assistance systems adas flexnoc interconnect semiconductor engineering soc architecture AI arteris ip ips K. Charles Janac on-chip memory interconnects logic IP modules SoC assembly topologies 5G mobility QoS

Architecting the Future of Deep Learning

Ty Garibay, CTO of Arteris IP, delivered the Keynote Address, “Architecting the Future of Deep Learning," which discusses the emerging system-on-chip (SoC) architectures enabling artificial intelligence, machine learning, and deep learning and how semiconductor technology can enable these innovations. Ty presented this keynote presentation at the eSilicon ASICs Unlock Deep Learning Innovation Seminar on March 14, 2018.

Topics: machine learning artificial intelligence eSilicon deep learning soc architecture