Arteris Articles

Semiconductor Engineering: Not Enough Respect for SoC Interconnect

K. Charles Janac, CEO at Arteris IP, shares his opinion in this week's blog appearing in Semiconductor Engineering:

Not Enough Respect for SoC Interconnect

 

July 30th, 2018 - By K. Charles Janac

Topics: semiconductor engineering arteris ip SoC semiconductor interconnects logic flexnoc interconnect topologies ips IP modules SoC assembly advanced driver assistance systems adas K. Charles Janac AI on-chip memory 5G mobility soc architecture QoS functional safety SoC security

Architecting the Future of Deep Learning

Ty Garibay, CTO of Arteris IP, delivered the Keynote Address, “Architecting the Future of Deep Learning," which discusses the emerging system-on-chip (SoC) architectures enabling artificial intelligence, machine learning, and deep learning and how semiconductor technology can enable these innovations. Ty presented this keynote presentation at the eSilicon ASICs Unlock Deep Learning Innovation Seminar on March 14, 2018.

Topics: eSilicon deep learning machine learning artificial intelligence soc architecture