Arteris Articles

Semiconductor Engineering: Chiplets, Faster Interconnects, More Efficiency

 Arteris IP's K. Charles Janac, president and CEO, chats with Ed Sperling at Hot Chips in this latest Semiconductor Engineering article:

Chiplets, Faster Interconnects, More Efficiency

August 22nd, 2019 - By Ed Sperling

Big chipmakers are turning to architectural improvements such as chipsets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency.

 

“Everyone is struggling with CCIX,” said K. Charles Janac, president and CEO of Arteris IP. “If you have an accelerator and two coherent dies, there are too many corner cases to get it to work easily. But now you can use 3D interconnects to hook together a planar CPU and a planar I/O. So this looks like one system to the software, and you have inter-chip links between the network on chip and different die. That way you can support non-coherent and coherent read/write across two die. It makes the interconnect more valuable, but it also makes it more complicated.”

“The memory controller and the NoC will have to be much more tightly integrated,” said Janac. “The problem is that neither one understands the QoS of the entire chip, and there aren’t any independent memory controller companies left. But memory traffic has to be better integrated to make this work.”

For more information, please visit our Resources page for free downloads of our technical papers; http://www.arteris.com/resources

Topics: SoC ArterisIP FlexNoC ncore cache coherent interconnect semiconductor engineering K. Charles Janac noc interconnect Hot Chips

Semiconductor Engineering: Where Should Auto Sensor Data Be Processed?

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments in this latest Semiconductor Engineering article:

Where Should Auto Sensor Data Be Processed?

August 1st, 2019 - By Ann Steffora Mutschler

Fully autonomous vehicles are coming, but not as quickly as the initial hype would suggest...

 

Indeed, when it comes to processing the sensor data, a number of approaches currently point to allowing for scaling between different ADAS levels, but which the best way to do that is still up for debate.

“There must be an architecture they can do that with, and the question is, ‘How do you do that?'” said Kurt Shuler, vice president of marketing at Arteris IP. “There’s a lot of interest in getting more hardware accelerators to manage the communications in software, and directly managing the memory. For this, cache coherence is growing in importance. But how do you scale a cache coherent system? This must be done in an organized way, as well as adding a whole bunch of masters and slaves to it, such as additional clusters.”

For more information, please download the Arteris FlexNoC Interconnect IP data sheet; https://www.arteris.com/download-flexnoc-datasheet

Topics: SoC autonomous driving ArterisIP FlexNoC semiconductor engineering LIDAR noc interconnect cache coherence hardware accelerators

Semiconductor Engineering: Edge Complexity To Grow For 5G

 Arteris IP's Kurt Shuler, Vice President of Marketing, quoted in the latest Semiconductor Engineering article:

Edge Complexity To Grow For 5G

July 2nd, 2019 - By Kevin Fogarty and Ed Sperling

Increased interdependence of technologies will drive different architectures and applications. 

It gets even more complicated in the automotive world than other any other markets because of safety-critical circuitry.

“You may have to reboot part of the chip for a failed operation, while keeping the rest of it operating in a safe state,” said Kurt Shuler, vice president of marketing at Arteris IP. “If you think about the space shuttle or a Boeing 777, the black boxes are 20 pounds. You can’t have that in a car. There is a lot of functional safety being done at the microprocessor level to save cost. That can be used to spy on what’s happening at the system level, so if there are problems you can isolate them and in a safe state and fail gracefully. If there is a transient error, you reboot.”

For more information, please download the Arteris FlexNoC AI Package data sheet; http://www.arteris.com/download-flexnoc-ai-package-datasheet

Topics: SoC functional safety FPGAs semiconductor engineering flexnoc ai package noc interconnect ML

SemiWiki: Intelligence in the Fog

Kurt Shuler, VP Marketing at Arteris IP, and Bernard Murphy (SemiWiki) discuss the hottest domains in tech today - AI and automotive in this new SemiWiki blog:

Intelligence in the Fog

June 12, 2019 - By Bernard Murphy

AI is creeping into places we might not expect, such as communication infrastructure. Bernard Murphy learns from Kurt Shuler how AI and AI-centric design methods are becoming more important in this surprising domain.

By now, you should know about AI in the cloud for natural language processing, image ID, recommendation, etc, etc (thanks to Google, Facebook, AWS, Baidu and several others) and AI on the edge for collision avoidance, lane-keeping, voice recognition and many other applications. But did you know about AI in the fog? First, a credit – my reference for all this information is Kurt Shuler, VP Marketing of Arteris IP. I really like working with these guys because they keep me plugged in to two of the hottest domains in tech today – AI and automotive. That and the fact that they’re really the only game in town for a commercial NoC solution, which means that pretty much everyone in AI, ADAS and a bunch of other fields (e.g. storage) is working with them.

For more information, please visit the Arteris IP AI package webpage: http://www.arteris.com/flexnoc-ai-package

Topics: SoC semiconductor automotive ADAS artificial intelligence semiwiki kurt shuler flexnoc ai package noc interconnect