Arteris Articles

Advanced SoC Interconnect IP Enables Greater Flexibility in an Era of Consolidation

I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year.  But before we let go of 2012, it’s important to reflect on the past year and see what it can teach us so we can make better business decisions moving forward.

Topics: NoC network-on-chip economics IP research semiconductor industry software SoC economics semiconductor industry economics ASICs ASIC design FPGAs field programmable gate arrays FPGA design intellectual property cores network-on-chip on-chip interconnect

Who REALLY calls the shots in chip design today?

Who REALLY calls the shots in chip design today?

That sounds like a stupid question. Who really calls the shots in chip design today? Well, chip designers of course.

Topics: economics semiconductor industry software SoC economics

IP Subsystems Are Nothing New

As featured in:
I’ve been hearing the term “IP subsystem” lately, and it seems to be the latest newfangled buzz word in the SoC semiconductor and IP industry, second only to “virtualization.” Much of the context for this growing interest in IP subsystems has been inspired from the work of Rich Wawrzyniak in his Semico Research report, “IP Subsystems: The Next IP Market Paradigm – October 2010.”

Topics: IP subsystems Semico TI OMAP ARC software analog