Ty Garibay, CTO at Arteris IP, adds his comments in this Semiconductor Engineering article:
Mesh Networking Grows For ICs
April 4th, 2018 - By Kevin Fogarty
Kurt Shuler, on Tue, Apr 10, 2018 @ 09:00 AM
Ty Garibay, CTO at Arteris IP, adds his comments in this Semiconductor Engineering article:
April 4th, 2018 - By Kevin Fogarty
Kurt Shuler, on Mon, Apr 02, 2018 @ 11:17 AM
Ty Garibay, CTO of Arteris IP stated, “Not only is it hard to justify the cost of these advanced nodes, it’s also hard to find people that can do it", in this Semiconductor Engineering article:
January 8th, 2018 - By Ann Steffora Mutchler
Kurt Shuler, on Wed, Jun 19, 2013 @ 04:34 PM
When discussing system-on-chip (SoC) design with my semiconductor design and software development peers, the conversation eventually gets around to the problem of, “There’s just too much IP!” The feelings I hear border on exasperation at the problem of integrating IP on today’s large SoCs. Engineers who were once paid to write lines of Verilog or C code from scratch are now spending much of their time tying together commercial hardware IP and the associated software. Their jobs have changed, and they’ve had to acquire new skills and new tools to be successful.
Kurt Shuler, on Mon, Dec 10, 2012 @ 06:00 AM
In September’s article, SMP, Asymmetric Multiprocessing, and the HSA Foundation, I explained why symmetric multiprocessing (SMP) architectures have been popular in PC and server markets, and why heterogeneous or asymmetric multiprocessing (AMP) has been the norm in mobility and consumer electronics markets. I also explained the trends that are leading PC and server markets to adopt heterogeneous architectures and introduced the HSA Foundation’s goal of making heterogeneous core chips easy to program.