Arteris Articles

Arteris IP Presents: Lessons Learned integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip

This presentation titled, "Lessons Learned integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip," presented by Kurt Shuler, VP of Marketing and Functional Safety Manager (FSM) at Arteris IP, and Diego Botero, Functional Safety Engineer at Arteris IP, to an audience at the ISO 26262 for Semiconductors (Munich) Conference.

Topics: functional safety ISO 26262 Systems-on-Chip FlexNoC kurt shuler accelerators ML/AI automotive chips IQPC

Forbes Technology Council: AI and the Third Wave of Silicon Processors

Ty Garibay, CTO at Arteris IP, authors this article for Forbes Technology Council:

Topics: interconnect IP Systems-on-Chip ArterisIP flexnoc interconnect AI GPUs ips Forbes

Asymmetric Multiprocessing with Heterogeneous Architectures: Use the Best Core for the Job

Often, the term “multiprocessing” is associated with tightly-coupled symmetric multiprocessing (SMP) architectures, due in large part to SMP’s prevalence in high-performance computing, x86/x64 servers, and PCs. Unfortunately, SMP’s incremental performance scaling for most applications decreases significantly with increasing numbers of cores. This lack of scalability has prompted many processor companies to avoid purely SMP solutions for their mobile and consumer electronics applications. Instead, they have implemented asymmetric multiprocessing (AMP) architectures to make more efficient use of silicon.

Topics: NoC Systems-on-Chip on-chip interconnect AMP symmetric multiprocessing HSA foundation OS

Busses, Crossbars and NoCs: The 3 Eras of SoC Interconnect History

Today the processor in your Blackberry or iPhone has more calculating power than a PC did only a decade ago. No surprise here. But how did this happen? What enabled this?
Topics: SoC Interconnect System-on-Chip NoC AMBA AHB AXI OCP network-on-chip network-on-chip Networks-On-Chip Systems-on-Chip ASB