Arteris Articles

Semiconductor Engineering: Adding NoCs To FPGA SoC

Ty Garibay, CTO at Arteris IP, comments on Bridging the gap:

Adding NoCs To FPGA SoCs 


June 28th,  2018 - By Ann Steffora Mutschuler

As complexity and device sizes rise, so does the need for an on-chip network.

Topics: NoC functional safety FPGA FlexNoC Ty Garibay arteris ip hardware SoCs SerDes digital 100-gigabit HBM2 CTO

Mesh Networking Grows For ICs

Ty Garibay, CTO at Arteris IP, adds his comments in this Semiconductor Engineering article:

Mesh Networking Grows For ICs

 

April 4th,  2018 - By Kevin Fogarty

Topics: SoC System-on-Chip on-chip interconnect Ty Garibay semiconductor engineering mesh networks 2.5D AI

Semiconductor Engineering: Getting Serious About Chiplets

Ty Garibay, CTO of Arteris IP stated, “Not only is it hard to justify the cost of these advanced nodes, it’s also hard to find people that can do it", in this Semiconductor Engineering article:

Getting Serious About Chiplets

 

January 8th,  2018 - By Ann Steffora Mutchler

Topics: System-on-Chip Ty Garibay semiconductor engineering chiplet