Arteris — The Company

Arteris is a start-up based in Paris, France and San José, California, U.S.A. The company was founded in 2003 by a group of semiconductor industry veterans. The company's focus is on the next-generation of challenges associated with System-on-Chip (SoC) design: on-chip communications, or Network-on-Chip (NoC).

Arteris is backed by an international set of venture capitalists and its management team brings experience from the communications, semiconductor, EDA, and IP industries.

The value proposition

Networking has been proven in the computer systems arena to be an extremely effective means of managing multi-level communications in distributed systems. In modern SoCs that integrate many different functions (IPs) into a single chip, needs are often similar, and the flexibility of a modular network represents a significant advantage when building highly complex designs with deep submicron technologies.

Traditional approaches to on-chip communication, that is, buses and their evolutions, do not scale with the increasingly complex IC evolution to 65 nm and 45 nm technologies. To solve complex SoC design challenges, a true Network-on-Chip (NoC) represents the breakthrough that meets system performance requirements and facilitates rapid design.

Instead of blindly adopting networking implementations used at the macro system level, Arteris has distilled the most applicable concepts and applied them in a way that suits the constraints of semiconductor design. After investing more than 15 years in on-chip communication design, Arteris introduced in 2005 the world's first commercial implementation of a NoC (Network-on-Chip), delivered in the form of Intellectual Property.

Key concepts for an innovative approach

The following key networking concepts are part of Arteris answer to the needs of SoC designers:

• Separation of the communication protocol and its hardware implementation into well-defined layers, to facilitate independent optimization of each layer.
• Packetization of transactions entering the NoC.
• Use of standardized packets for all information flows (data, control).
• Switch and link-style fabric(s) with QOS-aware packet routing.
• Flexible NoC topologies to match total system performance needs.

To this end, Arteris technology has been developed to provide the best possible wire efficiency, along with the warranty that the interconnect will not bottleneck the final SoC.

Arteris completes its offer with a powerful set of EDA tools to analyze and implement the best NoC solution for today's multimedia, telecommunication infrastructure and application processor chips.

Corporate backgrounder