Learn how FlexNoC Physical IP helps automate timing closure

By linking floorplan and technology process information to your FlexNoC architecture, FlexNoC Physical IP helps accelerate the timing closure process using automated pipeline insertion and by providing more complete inforation to the back-end SP&R flow.


  • Reduces or eliminates excessive SP&R iterations
  • Eliminates trial-and-error timing closure with automated pipeline configuration
  • Optimizes Quality-of-Results (QoR)
  • Enables physical optimization of the FlexNoC Physical interconnect separate from the rest of the SoC

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