AMBA CHI, ACE and CCIX interoperability for SoCs

AIP Ncore datasheet 2018-08-16-005-2552x3302-borderNcore 3 IP is a distributed heterogeneous cache coherent on-chip interconnect that enables SoC design teams to integrate processor clusters using the latest Arm® AMBA® CHI protocol (CHI Issue B), as well as the new CCIX protocol for multi-chip systems.

Includes:

  • Technology descriptions - CHI and ACE interoperability; CCIX protocol support for multi-chip systems; ISO 26262-compliant functional safety mechanisms; and more...
  • Benefits and advantages over other solutions
  • Customer and analyst viewpoints

 

 

    

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