CodaCache: Helping to Break the Memory Wall

ATP 5873961-94086 Arteris IP CodaCache - Tech Paper_Page_1-2552x3302-border-2584x3334-shadowDownload this 7-page technical paper titled, "CodaCache: Helping to Break the Memory Wall," authored by Kurt Shuler, VP of Marketing at Arteris IP, and JP Loison, Corporate Application Engineer at Arteris IP.

This paper describes a novel configurable last level cache IP, CodaCache, that provides an easy-to-use-integrate solution giving system architects the capability to configure and adapt the IP to their specific needs.Key technologies implemented in this IP are per-master way partitioning, scratchpad RAM allocation, AXI interfaces and functional safety mechanisms.

   

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