Most people think of NoCs as a high-performance technology, but they can also help designers reduce the power of their SoCs. The NoC is the heart of the chip, connecting to every core, so it is the natural place to implement power management. This presentation will explain how the Arteris NoC can efficiently manage SoC-level power, and how the NoC itself can be configured to minimize its own power draw, using examples from actual customer implementations of IoT processors.
This presentation announces a new IP product, FlexNoC Physical that can use placement data to estimate timing and automatically insert and configure pipeline stages to accelerate SoC timing closure. The continually evolving SoC floorplans and NoC topology are synchronized; enabling NoC IP physical timing and closure prior to merging with the millions of gates comprising the entire SoC. This physically aware IP aims to cut months from the timing closure process, lowering SoC costs and improving schedule predictability.