Do you want to contribute to the backbone of the some of the world's most popular SoCs? You will work with an expert team to design and deliver interconnect & memory hierarchy solutions. You'll design IPs created in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll have to create IPs that are matching the specifications before being released to our customers, to be part of a SoC for AI, IoT, automotive, mobile... our IPs are used everywhere!
- Write microarchitecture specification for highly configurable IPs.
- Develop or upgrade IPs RTL description with performance, power, area goals.
- Work closely with verification team to meet coverage requirements and fix issues.
- Communicate with Software, Modeling and Documentation teams about your changes to ensure product cohesion.
- Help improve and refine processes, methodologies, and metrics
Experience Requirements / Qualifications:
- 7+ years of industry experience as a Design Engineer
- Knowledge of Verilog or SystemVerilog.
- Knowledge of interconnect technology is a plus
- Knowledge of Cache architecture is a plus.
- Knowledge of AMBA protocols.
- Good written and verbal communication skills in both French and English
- Curious, autonomous, rigorous, and delivery-oriented with a commitment to quality and a thorough approach to the work.
- Proven ability to work well within a team
- Potential and desire for personal development and improvement
- Engineering Master's Degree