Senior Hardware Verification Engineer with Arteris, Inc. (Austin, TX)

Design verification of an interconnect, and successor products for system on chip devices. Responsible for additional short term and long term deliverables. Verify all facades of interconnects using digital design tools. Create design verification strategies and implement these strategies to achieve high quality of interconnect design. Apply VLSI tradeoffs including frequency vs. power, performance vs. area, and design complexity vs. verifiability. Use object oriented coding, scripting, and assembly language to write random and directed tests of correctness and performance of interconnects. Run interconnect simulations and debug failures using simulators and waveform viewers. Measure and analyze verification coverage of interconnects’ functional space and adjust test and test benches as needed.


Bachelor's or Master's degree in Electrical Engineering, Electronic Engineering, or related field.  Progressive, post-Bachelor experience is required (5 years following Bachelor's degree, or 3 years with Master's) which must include some experience with: C, Verilog, SystemVerilog, System on a Chip (SOC) verification, perl, shell scripting, AMBA bus, SystemVerilog assertions (SVA), UVM, and Verification planner.

Send Resumes to:

Saad Zahid, Arteris, 9601 Amberglen Blvd., Building G, Austin, TX 78729.

Arteris, Inc.

Worldwide Headquarters
591 W Hamilton Ave
Suite 250
Campbell, CA 95008


+1 408 470 7300