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EE Times article, IoT Was Interesting, But Follow the Money to AI Chips

Kurt Shuler, VP Marketing at Arteris IP, states that the upcoming change in focus will be so radical, that by 2025, a full five sixths of the growth in semiconductors is going to be the result of AI. 

February 2, 2019 - by Kurt Shuler

A few years ago there was a lot of buzz about IoT, and indeed it continues to serve a role, but looking out to 2025 the real dollar growth for the semiconductor industry is in algorithm-specific ASICs, ASSPs, SoCs, and accelerators for Artificial Intelligence (AI), from the data center to the edge.

Anyone tracking the industry closely knows how we got to this point. Designers were implementing IoT before it even became a “thing.” Deploying sensors and communicating on a machine-to-machine level to perform data analysis and implement functions based on structural or ambient environment and other parameters just seemed like a smart thing to do. The Internet just helped to do it remotely. Then someone latched onto the term “the Internet of things” and suddenly everyone’s an IoT silicon, software, or systems player.

Topics: eetimes automotive design SoCs AI semiconductor training kurt shuler autonomous vehicles data centers edge 28 nm

Semiconductor Engineering: The Race To Multi-Domain SoCs

 Arteris IP's CEO looks at how automotive and AI are Altering chip design in this article in Semiconductor Engineering;

The Race To Multi-Domain SoCs

February 7th,  2019 - By Ed Sperling

K. Charles Janac, president and CEO of Arteris IP, sat
down with Semiconductor Engineering to discuss the impact of automotive and AI on chip design. What follows are excerpts of that conversation.

SE: What do you see as the biggest changes over the next 12 to 24 months?
Janac: There are segments of the semiconductor market that are shrinking, such as DTV and simple IoT. Others are going through an investment phase, including automotive, AI/machine learning and China. You really want to be focused on those segments. 

SE: So does IP that’s being developed today look radically different than it did five years ago?
Janac:
Yes, everything is getting amazingly complex. What people are building right now are multi-domain SoCs. The CPU, which used to do all the work, does relatively less work. There are accelerators for vision and data analysis outside of the CPU subsystem. There are machine learning sections, some general-purpose, some very specific, all on-chip. There is a memory subsystem with very high-bandwidth memory and low latency. There also is functional safety. You need tremendous performance because a car is a supercomputer on wheels. The car has to be very efficient, because you need to deliver that compute power without water cooling. Power management becomes very sophisticated. And then there are functional safety and security subsystems to keep these safe from environmental and man-made issues.

SE: Where does the network on chip (NoC) fit into all of this?
Janac: All data goes through the NoC of the chip. There are opportunities for generating value from that. But the increase in complexity is increasing the number and sophistication of the interconnect parts of the chip. Before, you may have had networks on chip. Now you may have 20 or 30.

Topics: semiconductor AI automotive neural networks ML AI SoC Designers flexnoc ai package noc interconnect chiplets ADAS LIDAR

Semiconductor Engineering: ISO 26262:2018, 2nd Edition: What Changes?

 Arteris IP's Kurt Shuler, vice president of marketing, delivers a recent update for the ISO 26262 standard in this blog in Semiconductor Engineering;

ISO 26262:2018, 2nd Edition: What changes?

February 7th,  2019 - By Kurt Shuler

The safety standard is now clearer for IP-based designs and those happening across multiple companies.

If you’re involved somehow in design for automotive electronics, you probably have more than a cursory understanding of the ISO 26262 standard. What your organization is working from is most likely the 2011 definition. The most recent update is formally known as ISO 26262:2018, less formally as ISO 26262 2nd Edition.

Standards should evolve, but what changed and why? I’ve been a member of the ISO 26262 working group for many years, and particularly involved in how it should be interpreted for IP, and I’ve got to tell you, I have struggled. 

From my perspective, it was originally written around an implicit expectation that chips are built from scratch entirely within one organization, and this is a dated assumption. There was also not enough guidance for IP-based design or design distributed across multiple companies or sites. The workaround for an IP supplier has been to use the Safety Element out of Context (SEooC) mechanism. But this depends heavily on human interpretation, by the component vendor on what may be relevant to the integrator and vice-versa, with little guidance from the 2011 version of the standard. I complained (whined?) quite a bit to the committee about these problems and they eventually invited me to the working group. I wasn’t the only one confused and other people joined, and we seem to have had an impact; our efforts have resulted in a lot more clarification, organization and practical examples in the latest standard. I think the new Part 11 of the updated standard provides a lot more detail and useful examples for us in the semiconductor and semiconductor IP industry.

For more information about ISO 26262:2018 Part 11, download the 39-slide Arm TechCon presentation titled, “Fundamentals of ISO 26262 Part 11 for Semiconductors,” by Arteris IP Functional Safety Manager Alexis Boutillier and ResilTech Scientific Advisor Dr. Andrea Bondavalli, or watch my very popular SemiEngineering “Tech Talk: ISO 26262 Drilldown” video.

Topics: AI chips semiconductor AI automotive neural networks ML AI SoC Designers flexnoc ai package noc interconnect ISO 26262 certification

Arteris IP at DVCon 2019 Silicon Valley

Arteris IP at DVCon U.S. 2019 

Location: DoubleTree Hotel, 2050 Gateway Place, San Jose, CA
Poster Sessions: Tuesday, 26 February, 10:30am - 12:00pm, Gateway Foyer, 2nd level

Arteris IP is presenting the poster, "4.8 Flex-Checker: A One Stop Shop for all your Checkers: A Methodology for Elastic Score-boarding"

Topics: NoC semiconductor noc interconnect SoCs bandwidth latency performance hardware verification

SemiWiki: Why High-End ML Hardware Goes Custom

Kurt Shuler, VP Marketing at Arteris IP,  provides more insight into what's happening in this highly dynamic space in the latest SemiWiki blog written by Bernard Murphy (SemiWiki):

Why High-End ML Hardware Goes Custom

January 30th, 2019 - By Bernard Murphy

In a hand-waving way it’s easy to answer why any hardware goes custom (ASIC): faster, lower power, more opportunity for differentiation, sometimes cost though price isn’t always a primary factor. But I wanted to do a bit better than hand-waving, especially because these ML hardware architectures can become pretty exotic, so I talked to Kurt Shuler, VP Marketing at Arteris IP, and I found a useful MIT tutorial paper on arXiv. Between these two sources, I think I have a better idea now.

Start with the ground reality. Arteris IP has a bunch of named customers doing ML-centric design, including for example Mobileye, Baidu, HiSilicon and NXP. Since they supply network on chip (NoC) solutions to those customers, they have to get some insight into the AI architectures that are being built today, particularly where those architectures are pushing the envelope. What they see and how they respond in their products is revealing.

You can learn more about what Arteris IP is doing to support AI in these leading-edge ML design teams HERE. They certainly seem to be in a pretty unique position in this area.

 For more information, download this FlexNoC AI Package datasheet; http://www.arteris.com/flexnoc-ai-package

Topics: semiwiki kurt shuler NoC semiconductor AI chips flexnoc ai package noc interconnect ML-centric design accelerators

Arteris IP FlexNoC Interconnect Used by NationalChip for Set Top Box (STB) Chips

On-chip interconnect security technology enables more secure digital rights management (DRM)

CAMPBELL, Calif. – February 5, 2019 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that NationalChip has successfully produced satellite and terrestrial digital TV set top box (STB) systems-on-chip (SoC) using Arteris FlexNoC interconnect IP as the on-chip communication backbone.

Using Arteris IP FlexNoC’s unique security firewall technology, we were able to create a custom, in-hardware security system that implements DRM for our customers’ content while reducing the visible attack surfaces available to potential hackers. Arteris IP’s technology has allowed us to create high-value security features and reduce power consumption, which both add significant value to our STB products.”


Feng Ye, Chief Technology Officer, NationalChip

Topics: new customer FlexNoC china SoC security

Arteris IP Adds 20 New Licensees and Releases Three New Products in 2018

Network-on-Chip (NoC) semiconductor IP growth driven by customer development of new automotive, machine learning & data center systems-on-chip (SoCs)

CAMPBELL, Calif. – January 29, 2019 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip(NoC) interconnect intellectual property, today announced that the company added 20 new licensees for its Arteris IP Ncore®, FlexNoC®, CodaCache™, AI Package and PIANO®Interconnect IP products. Publicly announced Arteris customers added during 2018 include BaiduArbe Robotics, AutoChipsAutoTalksCanaan Creative, Enflame Technology, Iluvatar CoreX, and thirteen as yet undisclosed licensees. This is the highest number of new licensees added in one year in Arteris IP history.

In 2018, Arteris IP’s focus on automotive and artificial intelligence markets paid off with the highest number of new Arteris IP customers in history selecting our interconnect IP technology. This high rate of customer adoption allows us to invest more than any other company in the on-chip interconnect technologies needed for tomorrow’s SoC applications for artificial intelligence and machine learning, automated driving and data center acceleration.


K. Charles Janac, President and CEO Arteris IP

Topics: new customer FlexNoC Ncore flexnoc ai package

Arteris IP FlexNoC® Interconnect Licensed by NETINT Technologies for PCIe 4.0 Enterprise SSD Controllers

CAMPBELL, Calif. – January 15, 2019 – Arteris IP, the leading supplier of innovative, silicon-proven network-on-chip(NoC) interconnect intellectual property, today announced that NETINT Technologies has licensed Arteris IP FlexNoC Interconnect for use in its enterprise SSD storage system controllers with on-chip video processors.

For the G4 SoC inside each D400 SSD, the Arteris FlexNoC IP supports high bandwidth and data accuracy between the G4’s on-chip PCIe 4.0 interface and all internal subsystems. Arteris FlexNoC IP allows higher bandwidth and lower latency on-chip communications compared to other interconnect technologies, while increasing our development team’s efficiency, allowing us to create higher quality chips in less time.


Tao Zhong, CTONETINT Technologies

Topics: china new customer NETINT enterprise SSD FlexNoC

Arteris IP FlexNoC® Interconnect Licensed by Baidu for Kunlun AI Cloud Chips for Data Center

NoC interconnect IP optimizes dataflow for revolutionary Cloud-To-Edge artificial intelligence (AI) system-on-chip (SoC) architecture

CAMPBELL, Calif. – January 15, 2019 – Arteris IP, the leading supplier of innovative, silicon-proven network-on-chip(NoC) interconnect intellectual property, today announced that Baidu has licensed Arteris IP FlexNoC Interconnect for use in its high-performance Kunlun AI cloud chip for data center.

The Arteris FlexNoC interconnect IP helps us greatly by enabling not only high bandwidth on-chip communications but also load-balanced data traffic to off-chip memory, all while simplifying our backend timing closure. In addition, Arteris IP’s strong local support team has been a trusted partner in our AI chip development projects.


Jian Ouyang, Principal ArchitectBaidu

Topics: AI chips training chips neural network flexnoc ai package machine learning artificial intelligence Baidu china new customer

Arteris IP Announces New FlexNoC® 4 Interconnect IP with Artificial Intelligence (AI) Package

Industry leading commercial interconnect IP accelerates development of next-generation deep neural network (DNN) and machine learning systems

CAMPBELL, Calif. – October 31, 2018 – Arteris IP, the world’s leading supplier of silicon-proven commercial network-on-chip (NoC) interconnect intellectual property (IP)today announced the new Arteris IP FlexNoC version 4 interconnect IP and the companion AI Package. FlexNoC 4 and the AI Package (“FlexNoC 4 AI”) implement many new technologies that ease the development of today’s most complex AI, deep neural network (DNN), and autonomous driving systems-on-chip (SoC).

Numerous startups are attempting to develop SoCs for neural-network training and inference, but to be successful, they must have the interconnect IP and tools required to integrate such complex, massively parallel processors while meeting the requirements for high-bandwidth on-chip and off-chip communications. Arteris IP has the experience and interconnect IP to help these companies succeed, and FlexNoC 4 with the AI Package provides the features required for AI chips in an easy-to-use and highly configurable form.


Mike Demler, Senior Analyst and Senior EditorThe Linley Group & Microprocessor Report

Topics: AI chips SoC design training chips QoS neural network new product flexnoc ai package noc multicast mesh noc ring noc torus noc machine learning artificial intelligence