Latest News

SemiWiki: ML and Memories: A Complex Relationship

Kurt Shuler, VP Marketing at Arteris IP, helped Bernard Murphy (SemiWiki) learn the multiple ways that different types of memory need to connect to these accelerators in the latest SemiWiki blog:

ML and Memories: A Complex Relationship

March 13th, 2019 - By Bernard Murphy

How do AI architectures connect with memories? The answer is more complex than in conventional SoC architectures.

No, I’m not going to talk about in in-memory-compute architectures. There’s interesting work being done there but here I’m going to talk here about mainstream architectures for memory support in Machine Learning (ML) designs. These are still based on conventional memory components/IP such as cache, register files, SRAM and various flavors of off-chip memory, including not yet “conventional” high-bandwidth memory (HBM). However, the way these memories are organized, connected and located can vary quite significantly between ML applications.

For more information, please visit the Arteris IP AI package webpage:

Topics: semiconductor artificial intelligence semiwiki kurt shuler flexnoc ai package noc interconnect cache coherence

Arteris IP FlexNoC® Interconnect Licensed by DisplayLink for Systems-on-Chip

NoC interconnect enables greater chip design flexibility

CAMPBELL, Calif. April 16, 2019– Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that DisplayLink has licensed Arteris FlexNoC interconnect IP for use in its integrated chipsets.

FlexNoC enables DisplayLink to build on a predictable infrastructure for high frequency interconnects required in our SoC family." 

Ian Stacey, Vice President Silicon Engineering and Operations, DisplayLink

Topics: Arteris FlexNoC new customer automotive systems monitors chipsets high-bandwidth computing devices

Semiconductor Engineering: The Long and Detailed Road to Automotive Compliance

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments in the latest Semiconductor Engineering article.

The Long and Detailed Road to Automotive Compliance

April 4th, 2019 - By Ann Steffora Mutschler

Bringing an engineering organization up to speed with automotive safety standards is a long and arduous process. 

Complexity on complexity
Things can get complicated very fast. Kurt Shuler, vice president of marketing at Arteris IP, said it is not uncommon in SOTIF applications to hear, “‘I’m going to do a system and it’s got cameras, and it’s got radars, and the radars have cameras, and there are sensors.’ It’s very complicated. People ask us how to protect against this and that, and how to ensure this thing works and what can be done in the interconnect to help with that. So we get pulled into these really high-level questions. And because an interconnect is configurable IP, and each customer’s design is totally different, we also get pulled into discussions around the process aspect to ISO 26262 when using configurable IP as opposed to a hard macro. These companies are asking us 1,001 questions about that, and it really is difficult. What we generally have to do is agree upfront that we are responsible for a specific part of the specification. And as a safety element out of context, we are responsible for this type of analysis and this kind of stuff; here are our assumptions of use and everything; and we agree on this. Any other insights we give to them is something we do to help them, but it’s not necessarily part of a contract or that’s required. The reason to have that agreement up front is because a lot of these companies are new to automotive, and we have a lot of experience, but we don’t want to be an ISO 26262 consultancy.”

For more information, please click and download this presentation; ISO 26262: What to expect from your chip or IP provider:

Topics: SoC ISO 26262 automotive semiconductor engineering noc interconnect SOTIF (ISO 21448

Semiconductor Engineering: Racing To The Edge

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments in the latest Semiconductor Engineering article.

Racing To The Edge

April 9th, 2019 - By Susan Rambo and Ed Sperling

The race is on to win a piece of the edge despite the fact that there is no consistent definition of where the edge begins and ends or how the various pieces will be integrated or ultimately tested.

Safety lives at the edge
“The edge includes a lot of the stuff where people are most concerned about things that can kill you, like cars and robots and medical devices,” said Kurt Shuler, vice president of Arteris IP. “These things can kill you two ways. One is a cosmic ray and the traditional functional safety use case, where it flips a bit and then it goes awry. The other way is everything works as intended, however what it does and what it decides to do from its neural net application is the wrong thing. There’s not a cosmic ray. There’s not a hardware safety problem. The safety of the intended function is bad. (There is a new specification out for that, ISO/PAS 21448:2019 Road Vehicles — Safety of the Intended Functionality.)”

For more information on AI, please click on the Arteris FlexNoC AI Package webpage:

Topics: SoC ARM automotive semiconductor engineering safety noc interconnect edge ISO/PAS Intended functionality

Arteris IP is Hiring a Hardware Verification Engineer in Paris!

Featured Position!

Hardware Verification Engineer in Paris (Guyancourt), France

Do you want to contribute to the backbone of the some of the world's most popular SoCs? You will work with an expert team to design and deliver interconnect & memory hierarchy solutions. You'll verify designs created in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll have to ensure that our IPs are matching the specifications before been released to our customers, to be part of a SoC for AI, IoT, automotive, mobile... our IP is used everywhere!

Topics: hardware verification arteris ip RTL noc interconnect job SoC designs C/C++ Python

Arteris IP Awarded 1st Place for Technical Paper at Synopsys Users Group (SNUG) Silicon Valley 2019

Benny Winefeld, Solutions Architect at Arteris IP, Awarded 1st Place Best Paper Award at SNUG Silicon Valley 2019 

Arteris IP presented this technical paper, "Using Machine Learning for Characterization of NoC Components", on March 20, 2019.

Benny Winefeld, Solutions Architect at Arteris IP, accepted the 1st Place Best Paper Award from the SNUG Technical Committee during SNUG Silicon Valley. There were 29 papers that competed for the best paper award.

In the photo above, Benny receives the award from the SNUG committee, from left to right: Ken Nelson, VP Field Support Operations; Benny Winefeld, Solutions Architect, Arteris IP; Tony Todesco, SNUG SV Technical Chair, AMD; and Deirdre Hanford, Co-GM, Synopsys.

Topics: Synopsys NoC machine learning artificial intelligence Soft IP noc interconnect SNUG

Arteris IP FlexNoC® Interconnect Licensed by Horizon Robotics for ADAS Chips

NoC interconnect IP enables more efficient on-chip dataflow for neural networking processing chips and subsystems

CAMPBELL, Calif. — April 2, 2019 — Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual propertytoday announced that Horizon Robotics has licensed Arteris IP FlexNoC Interconnect for use in multiple ADAS chips.

Arteris IP’s FlexNoC interconnect allows us to more easily optimize and implement our chip architectures for ideal dataflow within our ADAS systems, ensuring processing elements avoid starvation and communications occur with minimum latency. We are happy to be working with the world leader in network-on-chip interconnect technology to develop our next generation of pioneering ADAS chips and systems.” 

Dr. Yu Kai, Founder and CEO, Horizon Robotics

Topics: automotive semiconductors Arteris FlexNoC new customer china advanced driver assistance systems adas artificial intelligence neural network automotive systems

Arteris® IP FlexNoC® Interconnect Licensed by Morningcore for Automotive LTE-V2X Modems for China Market

NoC interconnect ensures high data bandwidth and low latency on-chip communications

CAMPBELL, Calif. — March 26, 2019 — Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Morningcore Technology has licensed Arteris FlexNoC interconnect IP for use in its next-generation automotive LTE vehicle-to-vehicle / vehicle-to-infrastructure (V2X) communication modems.

The Arteris team has unique expertise in both automotive and wireless applications, and their technology and local support have been a perfect fit for our development team’s needs.” 

Zhigang Gu, Product Manager, Morningcore

Topics: automotive semiconductors Arteris FlexNoC new customer wireless mobility china automotive systems v2x

Sonics and Arteris IP Agree to Dismiss Litigation

Litigation is dismissed with prejudice with no funds changing hands

CAMPBELL, Calif. — March 21, 2019 Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Case # 11-cv-5311-SBA was dismissed with prejudice by the Northern District of California Court with support of all parties involved. This litigation was launched by Sonics Inc. in November of 2011 alleging infringement of seven Sonics patents by Arteris, Inc. Arteris vigorously denied any infringement while challenging the validity of Sonics’ patents. The case was stayed for patent re-examination by the US Patent and Trademark Office in June of 2014 and was dismissed in March of 2019. The stipulated dismissal with prejudice is now part of the public record.

Arteris IP will, as always, continue to compete strongly in the interconnect IP market for the benefit of the entire semiconductor industry and our nearly 120 customers.” 

K. Charles Janac, President and CEO, Arteris IP

Topics: sonics

Arteris IP FlexNoC Interconnect & Resilience Package Licensed by Vayyar Imaging for ISO 26262-Compliant 3D Imaging Chips for Automotive Systems

NoC interconnect enables high bandwidth and low latency on-chip communications while increasing functional safety diagnostics coverage

CAMPBELL, Calif. — March 19, 2019 Arteris IP, the leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Vayyar Imaging has licensed Arteris FlexNoC interconnect IP and the accompanying FlexNoC Resilience Package for use in its next-generation radio frequency (RF) 3D imaging chips for automotive systems.

Vayyar’s chip is the most advanced radar imaging SoC in the market today enabling real-time high-resolution 3D Point Cloud. Our chip requires the ability to transfer large amounts of data and make sure the highest safety standards are kept. Arteris NoC technology enables data protection mechanisms that increase the functional safety of our systems to meet the highest automotive safety standards.” 

Raviv Melamed, CEO and Co-Founder, Vayyar Imaging

Topics: SoC security new customer flexnoc resilience package ISO 26262 compliance ADAS systems RF automotive systems