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Semiconductor Engineering: Choosing Between CCIX and CXL

Kurt Shuler, vice president of marketing at Arteris IP participates in this Experts at the Table, Part 2 with Ed Sperling in this new Semiconductor Engineering article:

Choosing Between CCIX and CXL

May 19th, 2020 - By Ed Sperling

Experts at the Table, Part 2: What's right for one design may not be right for the next. Here's why.
 
Kurt Shuler, vice president of marketing at Arteris IP said, "When CCIX first came out, there was a lot of discussion about doing larger-scale, symmetric cache-coherent systems. But as you add in die or separate chips, and you have to increase memories and caches — and data for what’s going on in the different die, and locally storing that — there’s an architectural line where it doesn’t make much sense anymore. Are you actually losing more than you’re gaining? It’s really, really hard for architects to figure out where that hump is. Even if you have 20 years of experience as a cache-coherent architect, you can’t figure this out anymore in your head or by using Excel. That doesn’t work with CCIX and CXL".
 
To learn more, please click here for the Tech Talk CXL vs. CCIX video: https://www.arteris.com/blog/semiconductor-engineering-cxl-vs.-ccix-video 
 
Topics: SoC automotive CCIX NoC technology semiconductor engineering ADAS systems tech talk video kurt shuler noc interconnect CXL IP market asymmetric PHY cache coherent

Semiconductor Engineering: Spiking Neural Networks: Research Projects or Commercial Products?

Michael Frank, fellow and chief architect at Arteris IP is quoted in this new Semiconductor Engineering article:

Spiking Neural Networks: Research Projects or Commercial Products?

May 18th, 2020 - By Byron Moyer

Opinions differ widely, but in this space that isn't unusual.
 
SNN neurons typically are implemented in one of two ways. The approaches are motivated by analog implementations, although they can be abstracted into digital equivalents.  Arteris IP   fellow and chief architect Michael Frank refers to this as “emulation.” He points to several challenges for an analog implementation: “With analog, you would need to customize the model to the specific chip for inference. No two transistors are the same. And at 7 nm, you can’t do analog.”
 
Topics: analog SoC automotive neural networks NoC technology semiconductor engineering emulation noc interconnect IP market SNN multi-cast spike data

Arteris® IP FlexNoC® Interconnect and AI Package Licensed by Blue Ocean Smart System for AI Chips

State-of-the-art Network-on-Chip (NoC) interconnect enables optimized write broadcast dataflow for AI inference and training hardware accelerator chips

CAMPBELL, Calif. – May 19, 2020 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Blue Ocean Smart System has licensed Arteris FlexNoC Interconnect IP and the accompanying AI Package for use in next generation systems-on-chip (SoC) that hardware accelerate artificial intelligence (AI) neural network inference and training.

From prior experience, I knew that Arteris interconnect IP was the best solution to construct complex high frequency and high bandwidth on-chip interconnects that were backend friendly for easier timing closure. The addition of the AI Package allows us to finely tune our chip architecture using multicast write semantics which greatly reduce off-chip memory accesses while using little die area and consuming much less power. Our use of Arteris FlexNoC and the AI Package has been key to turning our architectural dreams into system-on-chip reality.”


John Rowland, President, Blue Ocean Smart

Topics: SoC NoC on-chip interconnect new customer memory machine learning neural network performance high-bandwidth Arteris IP FlexNoC interconnect AI inference accelerate

All About Circuits: The Role of Last-Level Cache Implementation for SoC Developers

Kurt Shuler, vice president of marketing at Arteris IP authored this new All About Circuits article:

The Role of Last-Level Cache Implementation for SoC Developers

May 13th, 2020 - By Kurt Shuler

There is a challenge for SoC developers to find ways to navigate the demand of memory in their design. This article looks at how a fourth, or last-level, cache can provide a solution.

So, what’s the best memory solution? For hints, we can look at what other companies are doing. Tear-down analyses have shown that Apple, for one, solves the speed mismatch problem by adding another cache. If a big company with nearly infinite R&D resources designs around its SoCs bottlenecks this way, it’s probably worth looking into. 
 
Topics: Apple SoC NoC technology CodaCache last level cache kurt shuler noc interconnect ML IP market security All About Circuits DSP

Semiconductor Engineering: Vehicle Communications Is Due For An Overhaul

Kurt Shuler, vice president of marketing at Arteris IP is quoted in this new Semiconductor Engineering article:

Vehicle Communications Is Due For An Overhaul

May 12th, 2020 - By Ann Steffora Mutschler

The Controller Area Network (CAN), one of the main communications networks in an automobile, is headed for a security overhaul — if not a wholesale replacement.
 
Kurt Shuler, vice president of marketing at  Arteris IP , likewise stressed the need for am architecture for security from the start. “Do as much as you can at the lowest possible level, because that’s where you can have the most control later. If you’re doing everything in software later, there are still ways around that. If you have things at the hardware level — and that’s where it comes to with the interconnects and the firewalls — if you have the physical mechanisms to stop traffic that shouldn’t be there during certain use cases and you can control that later when there’s new use cases, you’re covered. But it’s got to be built in an overall architecture, where the smallest parts are the SoC transistors. This equates to fire-walling, and either poisoning data that is suspect and letting it through or firing an interrupt up to the system that says, ‘Hey, I’m being hacked.’”
 
Topics: SoC automotive NoC technology semiconductor engineering kurt shuler data centers noc interconnect IP market security CAN BUS SoC transistors

Arteris® IP FlexNoC® Interconnect Licensed by Picocom for 5G New Radio Infrastructure Baseband SoCs

State-of-the-art Network-on-Chip (NoC) interconnect enables complex high-speed, yet flexible design

CAMPBELL, Calif. – May 12, 2020 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Picocom has licensed Arteris FlexNoC Interconnect IP for use in its upcoming 5G New Radio (5G NR) small cell baseband system-on-chip (SoC). Picocom specializes in 5G wireless baseband technologies for open small cell radio access networks.

Arteris interconnect IP was a smart choice to assist us in overcoming the design intricacies of the evolving 5G NR standard for our silicon. It is enabling us to manage our on-chip SoC bandwidth and complexity, whilst allowing us to retain design flexibility. In addition, it has helped us reduce development time, a crucial achievement in the fast-paced 5G NR market.”


Yingbo Jiang, CEO, Picocom

Topics: SoC NoC new customer enterprise SSD low power bandwidth performance high-bandwidth 5G Arteris IP FlexNoC interconnect base station wireless baseband

Semiconductor Engineering: Which Chip Interconnect Protocol is Better?

Kurt Shuler, vice president of marketing at Arteris IP participates in this Experts at the Table with Ed Sperling in this new Semiconductor Engineering article:

Which Chip Interconnect Protocol is Better?

May 11th, 2020 - By Ed Sperling

Experts at the Table: CXL and CCIX are different but it's not always clear which is the best choice.
 
"Everybody is circling around and trying to figure out what everybody else is doing, said Kurt Shuler, vice president of marketing at Arteris IP. CCIX is a little different. The idea there was that you would have one or more chips and they would all be one cache coherent system. So in the case of CXL, the coherency is all managed on the Xeon side, and that companion chip is always a slave. It’s different with CCIX. So if you do the bi-directional coherency, which is what people are interested in, it’s one big cache-coherent system".
 
To learn more, please click here for the Tech Talk CXL vs. CCIX video: https://www.arteris.com/blog/semiconductor-engineering-cxl-vs.-ccix-video 
 
Topics: SoC automotive CCIX NoC technology semiconductor engineering tech talk video kurt shuler data centers noc interconnect CXL IP market

Arteris® IP FlexNoC® Interconnect Again Licensed by NETINT Technologies for Codensity Enterprise SSD Controllers

State-of-the-art Network-on-Chip (NoC) technology enables next-generation of SSD controllers for high density real-time 4K H.265 video transcoding and storage

CAMPBELL, Calif. – March 24, 2020 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that NETINT Technologies has once again licensed Arteris IP FlexNoC Interconnect for use in its next-generation of enterprise solid state disk (SSD) storage system controllers with on-chip video encoding processors. NETINT’s first purchase of Arteris IP interconnect licenses was announced in January of 2019 (see, “Arteris IP FlexNoC® Interconnect Licensed by NETINT Technologies for PCIe 4.0 Enterprise SSD Controllers”).

Our Codensity G4 D400 SSDs were the industry’s first SSDs supporting a PCIe 4.0 interface, and our next-generation SSD controllers will push technology boundaries even more. Arteris FlexNoC interconnect IP has been critical to our products’ success because it enables the high bandwidth, low latency and data protection required for our systems. The flexibility of Arteris FlexNoC has allowed us to implement more sophisticated SoC architectures in less time that would otherwise be possible, thereby allowing us to create higher margin chips with less engineering effort.”


Tao Zhong, CEO, NETINT

Topics: SoC NoC new customer enterprise SSD low power performance high-bandwidth on-chip video encoding Arteris IP FlexNoC interconnect

Arteris® IP FlexNoC® Interconnect & Resilience Package Licensed by SiEngine for ISO 26262-Compliant Automotive Systems

State-of-the-art Network-on-Chip (NoC) interconnect increases chip performance, reduces design schedules, and provides functional safety mechanisms

CAMPBELL, Calif. – February 4, 2020 – Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that SiEngine has licensed the Arteris IP FlexNoC interconnect and the accompanying FlexNoC Resilience Package for use as the on-chip dataflow backbone of its next-generation automotive systems-on-chip (SoC).

We chose Arteris FlexNoC IP and the Resilience Package because of its integrated functional safety mechanisms and its ability to reduce on-chip routing congestion and increase performance. We are pleasantly surprised by the product’s rich functionality, flexible configuration and the excellent support from Arteris IP’s engineers, which allow us to achieve the specifically required functions with competitive performance.”


Xin-xin Yang, R&D Vice President, SiEngine

Topics: SoC NoC new customer automotive ISO 26262 resilience package performance AI chips ML/AI

Arteris IP Adds 17 New Licensees, Revenue Exceeds $31M in 2019

Network-on-Chip (NoC) semiconductor IP growth driven by customer development of new automotive, machine learning & data center systems-on-chip (SoCs)

CAMPBELL, Calif. — January 28, 2020 — Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that the company added 17 new licensees in 2019 for its Arteris® IP Ncore®, FlexNoC®, CodaCache®, AI Package, Resilience Package, and PIANO® Interconnect IP products. Of the 15 Arteris IP licensees publicly announced during 2019, three were acquired during the year (Bitmain, DisplayLink, and Vayyar) and fourteen are as yet undisclosed. The total number of Arteris IP customers reached 130.

“With our sizeable customer acquisition of 17 new licensees in 2019 and 20 new licensees in 2018, Arteris IP has increased interconnect market share against all alternatives. This growth allows Arteris IP to commercially invest more than anyone else in interconnect IP engineering and support to deliver best-in-class NoC technology to our customers. Arteris IP is increasingly the world’s trusted NoC interconnect engineering think tank able to augment an SoC ecosystem of related IP and EDA companies.”


K. Charles Janac, President and CEOArteris IP

Topics: new customer Ncore FlexNoC ncore cache coherent interconnect flexnoc ai package