Latest News

SemiWiki: Safety and Platform-Based Design

Kurt Shuler, VP Marketing at Arteris IP, updates Bernard Murphy of SemiWiki on some of the ways that safety and platform-based design interact, particularly where fail-operational functionality is required in autonomous or semi-autonomous systems, in this new SemiWiki blog:

Safety and Platform-Based Design

October 22nd, 2019 - By Bernard Murphy

Platform-based design, an approach to easily support multiple derivatives, opens some interesting new twists for safety-centric design. 

Bernard was at Arm TechCon as usual this year and one of the first panels he covered was close to the kickoff, hosted by Andrew Hopkins (Dir System Technology at Arm), Kurt Shuler (VP Marketing at Arteris IP) and Jens Benndorf (Managing Dir and COO at Dream Chip Technologies). The topic was implementing ISO 26262-compliant AI SoCs with Arm and Arteris IP, highly relevant since more and more of this class of SoC are appearing in cars. One thing that really stood out for me was the value of platform-based design in this area, something you might think would be old news for SoC design but which introduces some new considerations when safety becomes important.

You can learn more about this design by downloading the Arm TechCon presentation HERE.

Topics: SoC ARM semiconductor automotive automotive functional safety ArterisIP ISO 26262 compliance artificial intelligence AI semiwiki kurt shuler noc interconnect AI SoCs ASIL compliance

EE Times article, The Age of the Monster Chip

K. Charles Janac, President and CEO, at Arteris IP, authored this article on what is now defined as a "Monster Chip".

September 19, 2019 - by K. Charles Janac

What are the system designs that require a leap in SoC complexity? It’s not only big datacenter artificial intelligence (AI) chips, but also autonomous vehicles such as cars, trucks and drones; they are self-landing, reusable rockets; they are medical devices carrying out remote diagnostics; and they are connected machine tool controllers supporting smart manufacturing.

These chips are starting to be referred to as “Monster Chips” because of both the size and complexity.

Topics: semiconductor ADAS eetimes autonomous driving AI K. Charles Janac SoCs noc interconnect data center automation blockchain big chips

Semiconductor Engineering: In-System Networks Are Front And Center

 Arteris IP's Kurt Shuler, VP of Marketing, authored this article and offers his perspective on HotChips 2019 in this latest Semiconductor Engineering:

In-System Networks Are Front And Center

September 15th, 2019 - By Kurt Shuler

AI demands push innovation in design architectures and techniques.

 

This year’s HotChips conference at Stanford was all about artificial intelligence (AI) and machine learning (ML) and what particularly struck me, naturally because we’re in this business too, was how big a role on-chip networks played in some of the leading talks.

Giant leaps are being made in supporting new AI architectures, tuning them for optimum performance per milliwatt and embedding them effectively into traditional and novel SoC architectures.

You can learn more by reading my white paper titled, "Re-Architecting SoCs for the AI Era". Download is free; https://www.arteris.com/download-re-architecting-socs-for-the-ai-era

Topics: SoC functional safety ISO 26262 machine learning cache coherency semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448 Hot Chips bigger chips

Semiconductor Engineering: Autonomous Vehicles Are Reshaping The Tech World

 Arteris IP's Kurt Shuler, VP of Marketing, comments on ISO 26262 and the need to add SOTIF for the unknown-unkown errors in this latest Semiconductor Engineering article:

Autonomous Vehicles Are Reshaping The Tech World

September 5th, 2019 - By Kevin Fogarty

Even before fully autonomous vehicles blanket the road there is major upheaval at all levels of the industry.

 

Until recently, the V-system testing of ISO 26262 has been the primary functional safety method for verification and validation. It will continue to play that role, according to Kurt Shuler, vice president of marketing at Arteris IP, but it will be supplemented by other types of testing such as SOTIF (safety of the intended functionality, ISO 21448).

“SOTIF was a little controversial,” Shuler said. “It almost didn’t get passed because of what I call the philosophical element. It is designed to find faults when things are working correctly, but it also finds errors that you don’t know about. The way it goes about that is a little different from the usual approach, but there are also standards coming from SAE and others from ISO, so there will be plenty of competition for this kind of challenge to be able to verify probabilistic systems.”

For more information, please visit our Resources page for free downloads of our technical papers; http://www.arteris.com/resources

Topics: SoC ISO 26262 autonomous driving ArterisIP FlexNoC semiconductor engineering AI kurt shuler noc interconnect SOTIF (ISO 21448

SemiWiki: AI, Safety and the Network

Kurt Shuler, VP Marketing at Arteris IP, and Bernard Murphy (SemiWiki) discuss, 'What is driving the boom in AI-centric design', in this new SemiWiki blog:

AI, Safety and the Network

September 4th, 2019 - By Bernard Murphy

You probably know that Arteris IP is very active in AI and safety, leveraging their central value in network-on-chip (NoC) architectures. Bernard Murphy of SemiWiki blogged on Kurt Shuler's front-to-back white-paper to walking us through the essentials of AI, particularly machine learning (ML) and its application for example in cars.

Kurt also highlights an interesting point about this rapidly evolving technology. As we build automation from the edge to the fog to the cloud, functionality, including AI, remains quite fluid between levels. Kurt points out that this is somewhat mirrored in SoC design. In both cases architecture is constrained by need to optimize performance and minimize power across the system through intelligent bandwidth allocation and data locality. And for safety-critical applications, design and verification for safety around intelligent features must be checked not only within and between SoCs in the car but also beyond, for example in V2x communication between cars and other traffic infrastructure.

You can learn more by downloading this Arteris IP white paper titled, Re-Architecting SoCs for the AI Era: https://semiwiki.com/automotive/274598-ai-safety-and-the-network/

Topics: SoC functional safety ISO 26262 semiconductor automotive ADAS machine learning artificial intelligence semiwiki kurt shuler flexnoc ai package noc interconnect

Arteris IP Ncore® Cache Coherent Interconnect Licensed by Bitmain for Sophon TPU Artificial Intelligence (AI) Chips

Network-on-chip (NoC) interconnect enables faster performance and lower die area for Tensor Processing Unit (TPU) AI/ML applications

CAMPBELL, Calif. June 9, 2019– Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Bitmain has licensed Arteris Ncore Cache Coherent Interconnect IP for use in its next-generation Sophon Tensor Processing Unit (TPU) systems-on-chip (SoCs) for the scalable hardware acceleration of artificial intelligence (AI) and machine learning (ML) algorithms.

Our choice of interconnect IP became more important as we continued to increase the complexity and performance of Sophon AI SoCs. The Arteris Ncore cache coherent interconnect IP allowed us to increase our on-chip bandwidth and reduce die area, while being easy to implement in the backend. The Ncore IP’s configurability helped us optimize the die area of our SoC, which permits us to offer our users more performance at lower cost.”


Haichao Wang, CEO, Bitmain

Topics: SoC NoC new customer performance AI chips ML/AI scalable hardware on-chip bandwidth

Arteris IP FlexNoC® Interconnect Implemented in Uhnder Digital Automotive Radar-on-Chip

Austin-based startup uses Arteris IP interconnect to optimize on-chip communications for automotive radar-on-chip (RoC) systems

CAMPBELL, Calif. June 25, 2019– Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Uhnder’s new automotive radar-on-chip (RoC) uses the Arteris FlexNoC IP as the on-chip interconnect.

Our choice of on-chip interconnect IP was very important to our success because of the unprecedented extent of on-chip integration and our huge bandwidth requirements. The Arteris FlexNoC interconnect IP helped us to surpass our performance goals while avoiding routing congestion in our tightly integrated single-chip radar.”


Manju Hedge, CEO and Cofounder, Uhnder

Topics: SoC NoC new customer machine learning autonomous driving flexnoc interconnect ML/AI on-chip communications automotive radar

Arteris® IP FlexNoC® Interconnect Licensed by Achronix for New Speedster®7t FPGA family

Network-on-chip (NoC) interconnect enables ASIC-like performance for Speedster7t FPGA family

CAMPBELL, Calif. — June. 18, 2019 — Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Achronix Semiconductor Corporation has licensed Arteris FlexNoC interconnect IP for use in its new Speedster7t FPGA family – based on a new, highly optimized architecture – that goes beyond traditional FPGA solutions featuring ASIC-like performance, FPGA adaptability and enhanced functionality to streamline designs.

Our new Speedster7t FPGA family requires extremely high on-chip bandwidth and advanced dataflow arbitration to make possible ASIC-class machine learning processing. The Arteris FlexNoC IP is the optimal interconnect to meet these demands, especially with the advanced process technology nodes and multi-gigahertz frequencies we are dealing with."


Steve Mensor, Vice President of Marketing, Achronix

Topics: SoC FPGA new customer machine learning artificial intelligence flexnoc interconnect ML/AI Achronix

Silicon-Proven Arteris IP Ncore ® Cache Coherent Interconnect Implemented in Toshiba ISO 26262-Compliant ADAS Chip

Toshiba tapes out next-generation automotive ADAS system-on-chip (SoC) using mature network-on-chip interconnect technology

CAMPBELL, Calif. — June. 11, 2019 — Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect semiconductor intellectual property, today announced that Toshiba has taped out its next generation automotive advanced driver assistance system (ADAS) chip using the Arteris IP Ncore Cache Coherent and FlexNoC®non-coherent interconnect with the associated Resilience Package.

Our use of the uniquely flexible Ncore cache coherent interconnect IP helped us to more quickly design and implement our next generation automotive ADAS chips while allowing us to increase hardware diagnostic coverage for ISO 26262 compliance. The Arteris IP team was very helpful in guiding us on the interconnect configuration to optimize system performance and hardware diagnostic coverage using the integrated functional safety mechanisms. Working with the highly professional Arteris team and their world class interconnect IP has helped us meet our performance requirements and schedule, while adding valuable capabilities that would not be possible with other interconnects.


Nobuaki Otsuka, Technology Executive at Electronic Device & Storage Corporation, Toshiba

Topics: SoC ISO 26262 automotive semiconductors japan flexnoc resilience package ADAS cache coherent interconnect advanced driver assistance systems adas imaging processor ncore cache coherent interconnect

Arteris IP and Wave Computing Collaborate on Reference Architecture for Enterprise Dataflow Platform

The Arteris FlexNoC Artificial Intelligence (AI) Package Coupled with Wave Computing's AI Systems and IP Technology Create a Unified Platform Optimized for AI Data Processing 

CAMPBELL, Calif. — May 21, 2019  Arteris IP, the world’s leading supplier of innovative silicon-proven network-on-chip (NoC) interconnect intellectual property (IP), and Wave Computing®, the Silicon Valley company accelerating artificial intelligence (AI) from the datacenter to the edge, are collaborating to create a blueprint that can help customers overcome compute-to-memory design challenges. Additionally, Wave Computing is licensing Arteris IP’s Ncore Cache Coherent Interconnect, FlexNoC interconnect IP, and its accompanying FlexNoC AI Package for use in the AI-enabled chips that fuel Wave Computing’s data center systems products. By working together to assimilate each other’s technology attributes, Wave Computing and Arteris can ensure the seamless flow of information enterprise-wide, helping speed time-to-insight.

Wave and Arteris have complementary compute and networking technologies that, when packaged together, address some of the key challenges facing system-on-chip designers today such as shorter product cycles and rapidly increasing product complexity. The world of AI demands greater compute power. Working with Arteris allows us to design a scalable data platform with blazing-fast performance at a cost-effective price that helps customers accelerate insight from the edge to the data center.”


Steve Brightfield, Senior Director, Strategic AI IP Marketing, Wave Computing

Topics: Arteris FlexNoC new customer artificial intelligence ncore cache coherent interconnect flexnoc ai package noc interconnect SoC designs datacenters