Latest News

Arteris IP is Hiring in Campbell, CA! Senior Software Engineering Manager

Featured Position!

Senior Software Engineering Manager in Campbell, CA

We are looking for an experienced Senior Software Engineering Manager who will report to the VP of Engineering. 

You, as a successful candidate, are dynamic and self-motivated with excellent organizational, and technical skills who can effectively communicate across all levels of management. The ideal candidate will be an experienced leader who is visionary, strategic, technology savvy and skilled in contemporary software technologies and architectures. You will own and drive both development and quality engineering across multiple development teams.

Candidates must have the ability to influence thinking or gain acceptance of others in potentially sensitive situations. A thorough understanding of product development and excellent people management skills is also critical.

Topics: software jobs artificial intelligence arteris ip noc interconnect job SoC designs C++ Java

Arteris IP Ncore® Cache Coherent Interconnect Licensed by Bitmain for Sophon TPU Artificial Intelligence (AI) Chips

Network-on-chip (NoC) interconnect enables faster performance and lower die area for Tensor Processing Unit (TPU) AI/ML applications

CAMPBELL, Calif. June 9, 2019– Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Bitmain has licensed Arteris Ncore Cache Coherent Interconnect IP for use in its next-generation Sophon Tensor Processing Unit (TPU) systems-on-chip (SoCs) for the scalable hardware acceleration of artificial intelligence (AI) and machine learning (ML) algorithms.

Our choice of interconnect IP became more important as we continued to increase the complexity and performance of Sophon AI SoCs. The Arteris Ncore cache coherent interconnect IP allowed us to increase our on-chip bandwidth and reduce die area, while being easy to implement in the backend. The Ncore IP’s configurability helped us optimize the die area of our SoC, which permits us to offer our users more performance at lower cost.”


Haichao Wang, CEO, Bitmain

Topics: SoC NoC new customer performance AI chips ML/AI scalable hardware on-chip bandwidth

Semiconductor Engineering: Edge Complexity To Grow For 5G

 Arteris IP's Kurt Shuler, Vice President of Marketing, quoted in the latest Semiconductor Engineering article:

Edge Complexity To Grow For 5G

July 2nd, 2019 - By Kevin Fogarty and Ed Sperling

Increased interdependence of technologies will drive different architectures and applications. 

It gets even more complicated in the automotive world than other any other markets because of safety-critical circuitry.

“You may have to reboot part of the chip for a failed operation, while keeping the rest of it operating in a safe state,” said Kurt Shuler, vice president of marketing at Arteris IP. “If you think about the space shuttle or a Boeing 777, the black boxes are 20 pounds. You can’t have that in a car. There is a lot of functional safety being done at the microprocessor level to save cost. That can be used to spy on what’s happening at the system level, so if there are problems you can isolate them and in a safe state and fail gracefully. If there is a transient error, you reboot.”

For more information, please download the Arteris FlexNoC AI Package data sheet; http://www.arteris.com/download-flexnoc-ai-package-datasheet

Topics: SoC functional safety FPGAs semiconductor engineering flexnoc ai package noc interconnect ML

Arteris IP FlexNoC® Interconnect Implemented in Uhnder Digital Automotive Radar-on-Chip

Austin-based startup uses Arteris IP interconnect to optimize on-chip communications for automotive radar-on-chip (RoC) systems

CAMPBELL, Calif. June 25, 2019– Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Uhnder’s new automotive radar-on-chip (RoC) uses the Arteris FlexNoC IP as the on-chip interconnect.

Our choice of on-chip interconnect IP was very important to our success because of the unprecedented extent of on-chip integration and our huge bandwidth requirements. The Arteris FlexNoC interconnect IP helped us to surpass our performance goals while avoiding routing congestion in our tightly integrated single-chip radar.”


Manju Hedge, CEO and Cofounder, Uhnder

Topics: SoC NoC new customer machine learning autonomous driving flexnoc interconnect ML/AI on-chip communications automotive radar

Arteris® IP FlexNoC® Interconnect Licensed by Achronix for New Speedster®7t FPGA family

Network-on-chip (NoC) interconnect enables ASIC-like performance for Speedster7t FPGA family

CAMPBELL, Calif. — June. 18, 2019 — Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect intellectual property, today announced that Achronix Semiconductor Corporation has licensed Arteris FlexNoC interconnect IP for use in its new Speedster7t FPGA family – based on a new, highly optimized architecture – that goes beyond traditional FPGA solutions featuring ASIC-like performance, FPGA adaptability and enhanced functionality to streamline designs.

Our new Speedster7t FPGA family requires extremely high on-chip bandwidth and advanced dataflow arbitration to make possible ASIC-class machine learning processing. The Arteris FlexNoC IP is the optimal interconnect to meet these demands, especially with the advanced process technology nodes and multi-gigahertz frequencies we are dealing with."


Steve Mensor, Vice President of Marketing, Achronix

Topics: SoC FPGA new customer machine learning artificial intelligence flexnoc interconnect ML/AI Achronix

EE Times article, SoC Interconnect: Don't DIY!

Kurt Shuler, VP Marketing at Arteris IP, explains why a DIY approach to building your own configurable interconnect IP product is not as easy as one may think.

June 13, 2019 - by Kurt Shuler

The recent market consolidation might have some companies considering whether this is a do-it-yourself (DIY) project that your company should consider taking on. Whether it’s a simple crossbar switch or a full-function network-on-chip (NoC) architecture for advanced SoCs, all that’s needed are the right people with the right knowledge and a big budget; eventually, it could happen. But the question isn’t can you do it? It’s should you do it?

Topics: semiconductor eetimes autonomous vehicles AI automotive design SoCs kurt shuler noc interconnect ML/AI

SemiWiki: Intelligence in the Fog

Kurt Shuler, VP Marketing at Arteris IP, and Bernard Murphy (SemiWiki) discuss the hottest domains in tech today - AI and automotive in this new SemiWiki blog:

Intelligence in the Fog

June 12, 2019 - By Bernard Murphy

AI is creeping into places we might not expect, such as communication infrastructure. Bernard Murphy learns from Kurt Shuler how AI and AI-centric design methods are becoming more important in this surprising domain.

By now, you should know about AI in the cloud for natural language processing, image ID, recommendation, etc, etc (thanks to Google, Facebook, AWS, Baidu and several others) and AI on the edge for collision avoidance, lane-keeping, voice recognition and many other applications. But did you know about AI in the fog? First, a credit – my reference for all this information is Kurt Shuler, VP Marketing of Arteris IP. I really like working with these guys because they keep me plugged in to two of the hottest domains in tech today – AI and automotive. That and the fact that they’re really the only game in town for a commercial NoC solution, which means that pretty much everyone in AI, ADAS and a bunch of other fields (e.g. storage) is working with them.

For more information, please visit the Arteris IP AI package webpage: http://www.arteris.com/flexnoc-ai-package

Topics: SoC semiconductor automotive ADAS artificial intelligence semiwiki kurt shuler flexnoc ai package noc interconnect

Silicon-Proven Arteris IP Ncore ® Cache Coherent Interconnect Implemented in Toshiba ISO 26262-Compliant ADAS Chip

Toshiba tapes out next-generation automotive ADAS system-on-chip (SoC) using mature network-on-chip interconnect technology

CAMPBELL, Calif. — June. 11, 2019 — Arteris IP, the world’s leading supplier of innovative, silicon-proven network-on-chip (NoC) interconnect semiconductor intellectual property, today announced that Toshiba has taped out its next generation automotive advanced driver assistance system (ADAS) chip using the Arteris IP Ncore Cache Coherent and FlexNoC®non-coherent interconnect with the associated Resilience Package.

Our use of the uniquely flexible Ncore cache coherent interconnect IP helped us to more quickly design and implement our next generation automotive ADAS chips while allowing us to increase hardware diagnostic coverage for ISO 26262 compliance. The Arteris IP team was very helpful in guiding us on the interconnect configuration to optimize system performance and hardware diagnostic coverage using the integrated functional safety mechanisms. Working with the highly professional Arteris team and their world class interconnect IP has helped us meet our performance requirements and schedule, while adding valuable capabilities that would not be possible with other interconnects.


Nobuaki Otsuka, Technology Executive at Electronic Device & Storage Corporation, Toshiba

Topics: SoC ISO 26262 automotive semiconductors japan flexnoc resilience package ADAS cache coherent interconnect advanced driver assistance systems adas imaging processor ncore cache coherent interconnect

Semiconductor Engineering: Machine Learning Drives High-Level Synthesis Boom

 Arteris IP's Kurt Shuler, Vice President of Marketing, quoted in the latest Semiconductor Engineering article:

Machine Learning Drives High-Level Synthesis Boom

June 6th, 2019 - By Kevin Fogarty

When a  company puts together a software/hardware design team, it's not a bad idea to make sure where the final responsibility lies.

Asking the right questions
“In China I had a long conversation with the hardware engineer about what we were trying to do, and it eventually became clear he was not the one calling the shots,” said Kurt Shuler, vice president of marketing at Arteris IP. “It was the software architect calling the shots, so we all got together and that let us move forward once I realized the chip was defined by the algorithm, not the other way around.

”But the software architect doesn’t always have a good feel for the hardware. “The other problem we had was that, often, a software architect won’t be that good at abstracting down to the transistor level, and the hardware architect may not be good at abstracting up to the software, so you have to kind of walk them through that,” said Shuler.

Insisting on tight integration and optimization of software with hardware also may be a good way to coordinate development, but it doesn’t always reflect realistic performance requirements. Shuler noted that one way to help customers think about the problem is, rather than asking the hardware architect what would happen if the chip didn’t live up to expectations, to ask what the impact on the device would be if they were to remove the chip and replace it with an off-the-shelf inference chip that would have been completely generic to the application.

For more information, please download the Arteris FlexNoC Interconnect IP data sheet; https://www.arteris.com/download-flexnoc-datasheet

Topics: SoC semiconductor engineering noc interconnect ML software architects

Arteris IP and Wave Computing Collaborate on Reference Architecture for Enterprise Dataflow Platform

The Arteris FlexNoC Artificial Intelligence (AI) Package Coupled with Wave Computing's AI Systems and IP Technology Create a Unified Platform Optimized for AI Data Processing 

CAMPBELL, Calif. — May 21, 2019  Arteris IP, the world’s leading supplier of innovative silicon-proven network-on-chip (NoC) interconnect intellectual property (IP), and Wave Computing®, the Silicon Valley company accelerating artificial intelligence (AI) from the datacenter to the edge, are collaborating to create a blueprint that can help customers overcome compute-to-memory design challenges. Additionally, Wave Computing is licensing Arteris IP’s Ncore Cache Coherent Interconnect, FlexNoC interconnect IP, and its accompanying FlexNoC AI Package for use in the AI-enabled chips that fuel Wave Computing’s data center systems products. By working together to assimilate each other’s technology attributes, Wave Computing and Arteris can ensure the seamless flow of information enterprise-wide, helping speed time-to-insight.

Wave and Arteris have complementary compute and networking technologies that, when packaged together, address some of the key challenges facing system-on-chip designers today such as shorter product cycles and rapidly increasing product complexity. The world of AI demands greater compute power. Working with Arteris allows us to design a scalable data platform with blazing-fast performance at a cost-effective price that helps customers accelerate insight from the edge to the data center.”


Steve Brightfield, Senior Director, Strategic AI IP Marketing, Wave Computing

Topics: Arteris FlexNoC new customer artificial intelligence ncore cache coherent interconnect flexnoc ai package noc interconnect SoC designs datacenters