Arteris news and press coverage

Arteris News

Montage Technology Licenses Arteris FlexNoC Interconnect IP for Set-Top Box (STB) Systems-on-Chip (SoCs)

4 August 2015

Montage Technology Licenses Arteris FlexNoC Interconnect IP for Set-Top Box (STB) Systems-on-Chip (SoCs)
PRWeb, Kurt Shuler

Network-on-chip interconnect IP enables optimal DRAM efficiency and quality-of-service (QoS)

Which Process, Material, IP?

30 July 2015

Which Process, Material, IP?
Semiconductor Engineering (US), Ed Sperling

More choices and market consolidation are raising questions about integrity and completeness of ecosystems with each new process node and process flavor.

7 Ways To Assess Semiconductor IP Quality

29 July 2015

7 Ways To Assess Semiconductor IP Quality
Semiconductor Engineering (US), Kurt Shuler

Assessing IP quality should be top priority for SoC design teams weighing time-to-market risk factors against configurability

The Hard Facts about Soft Interconnect IP

27 July 2015

The Hard Facts about Soft Interconnect IP
Design & Reuse (France), Charlie Janac

Building world-class Network-on-Chip interconnect IP and configuration tools is difficult, time consuming and capital intensive

Experts at the Table: Speeding Up Analog

16 July 2015

Experts at the Table: Speeding Up Analog
Semiconductor Engineering (US), Ann Steffora Mutschler

Modeling; spreading out tasks; digitally-assisted analog; don’t live in digital process nodes.

Moore Memory Problems

9 July 2015

Moore Memory Problems
Semiconductor Engineering (US), Brian Bailey

The scaling of the 6T SRAM cell is slowing and the surrounding circuitry is getting more complex, so more of the die will be taken up by SRAM at future nodes.

Experts at the Table: IP Integration Challenges Increase

8 July 2015

Experts at the Table: IP Integration Challenges Increase
Semiconductor Engineering (US), Ed Sperling

More characterization needed for finFET-based designs; why consolidation is both good and bad for IP vendors.

Sequans Licenses Arteris FlexNoC Interconnect IP for Low Power LTE IoT SoC

7 July 2015

Sequans Licenses Arteris FlexNoC Interconnect IP for Low Power LTE IoT SoC
PRWeb, Kurt Shuler

Network-on-chip interconnect fabric to help boost cloud services IoT strategy

Mobile Security And The IoE

6 July 2015

Mobile Security And The IoE
Semiconductor Engineering (US), Ernest Worthman

Keeping the IoE mobility secure is no small challenge.

Is Interconnect Ready for the Post-mobile SoCs?

28 June 2015

Is Interconnect Ready for the Post-mobile SoCs?
SemiWiki (US), Majeed Ahmad

The interconnect technology is one of the unsung heroes of the system-on-chip (SoC) revolution. It's the on-chip networking fabric that is used to link various IP cores on an SoC floorplan.

Ten reasons interconnect matters

26 June 2015

Ten reasons interconnect matters
Design & Reuse (France), Jonah Probell

Interconnect is the Rodney Dangerfield of IP blocks. It gets no respect. To the uninitiated, an interconnect fabric is a bunch of wires. The interconnect in modern chips is comprised of millions of gates of standard cells.

What Is A System Now?

25 June 2015

What Is A System Now?
Semiconductor Engineering (US), Ann Steffora Mutschler

s designs become part of connected networks, so do the requirements for what’s needed to make it work properly.

More Data, Different Approaches

25 June 2015

More Data, Different Approaches
Semiconductor Engineering (US), Ed Sperling

As the amount of data in designs explodes, Big Data tools and techniques are being added into EDA and manufacturing.

Accelerating ISO 26262 Automotive Functional Safety Certification

9 June 2015

Accelerating ISO 26262 Automotive Functional Safety Certification
DAC 2015 (US), Monica Tang

The challenges in certifying SoCs for ISO 26262 automotive functional safety present a high barrier to entry for design teams attempting to cross over from other segments like mobility or consumer.

Executive Insight: Charles Janac

8 June 2015

Executive Insight: Charles Janac
Semiconductor Engineering (US), Ed Sperling

Arteris’ chairman and CEO talks about what’s behind the industry consolidation, what’s changing in automotive, and where the holes are in the IoT.

Experts at the Table: IP Market Shifts Direction

3 June 2015

Experts at the Table: IP Market Shifts Direction
Semiconductor Engineering (US), Ed Sperling

Even standard IP is getting customized by large vendors as consolidation continues to change the fundamental premise for third-party IP.

SoCの低消費電力設計ノウハウ [Modular Approach to SoC Interconnect Slashes Power Consumption via Unit-Level Clock Gating]

29 May 2015

SoCの低消費電力設計ノウハウ [Modular Approach to SoC Interconnect Slashes Power Consumption via Unit-Level Clock Gating]
EDN Japan (Japan), Jonah Probell

ユニットレベルのクロックゲーティングで消費電力が下がる! モジュール方式のSoCインターコネクト (1/4) SoCの低消費電力化で見過ごされがちな“インターコネクト”。ここでは、SoCのダイサイズを縮小し、消費電力を低減できるモジュール方式のSoCインターコネクト技術について紹介する。

What’s Different At 16/14nm?

28 May 2015

What’s Different At 16/14nm?
Semiconductor Engineering (US), Ed Sperling

FinFET-based design is expensive and difficult, with parts of road map still under construction, but progress is being made.

Tear Down The Wall Between Front-End And Back-End Teams

28 May 2015

Tear Down The Wall Between Front-End And Back-End Teams
Semiconductor Engineering (US), Kurt Shuler

It’s increasingly easy to design a chip that’s impossible to manufacture.

Arteris FlexNoC Fabric IP Implemented in New Toshiba 4K Ultra HD Televisions

26 May 2015

Arteris FlexNoC Fabric IP Implemented in New Toshiba 4K Ultra HD Televisions
PRWeb, Kurt Shuler

Enables faster design time and time to market for DTV systems-on-chip

It’s Time to Stop Kicking the EDA Dog

25 May 2015

It’s Time to Stop Kicking the EDA Dog
EE Times (US), Kurt Shuler

It's incumbent on IP vendors to deliver higher quality designs that enable a smoother back-end process.

The 7 levels of IP verification

15 May 2015

The 7 levels of IP verification
EDN (US), Charlie Janac

The quality of semiconductor intellectual property (IP) is a major issue for design teams utilizing third-party sources for portions of their SoCs. Quality is even more critical for highly configurable types of IP because customers license it specifically to address the unique requirements of their systems and markets.

Network-on-Chip Gets Automated Timing Closure

6 May 2015

Network-on-Chip Gets Automated Timing Closure
Electronic Design (US), William Wong

The new FlexNoC Physical product is designed for automated timing closure with FlexNoC designs. It can save as much as three months of work due to timing closures on complex SoC designs (Fig. 1). This in turn reduces the cost of the SoC.

Automating Timing Closure Using Interconnect IP, Physical Information

29 April 2015

Automating Timing Closure Using Interconnect IP, Physical Information
SemiWiki (US), Majeed Ahmad

Timing closure is a “tortoise” for some system-on-chip (SoC) designers just the way many digital guys call RF design a “black art”. Chip designers often tell horror stories of doing up to 20 back-end physical synthesis place & route (SP&R) iterations with each iteration taking a week or more.

Pressure Builds To Revamp The Design Flow

23 April 2015

Pressure Builds To Revamp The Design Flow
Semiconductor Engineering (US), Ed Sperling

Some contend it needs to be rebuilt from scratch, others believe it can be tweaked and fixed.

Arteris Delivers FlexNoC Physical™ Interconnect IP to Accelerate SoC Layout

22 April 2015

Arteris Delivers FlexNoC Physical™ Interconnect IP to Accelerate SoC Layout
PRWeb, Kurt Shuler

Physically-aware IP leverages on-chip interconnect architecture for automated timing closure, first-pass place & route success

Rockchip Bets on Arteris FlexNoC Interconnect IP to Leapfrog SoC Design

19 April 2015

Rockchip Bets on Arteris FlexNoC Interconnect IP to Leapfrog SoC Design
SemiWiki (US), Majeed Ahmad

China was a virgin territory for Arteris Inc. before July 19, 2012 when Fuzhou Rockchip Electronics announced that it has licensed the Arteris FlexNoC network-on-chip (NoC)-based interconnect IP technology for its multicore SoCs for budget Android tablets.

Arteris Delivers FlexNoC Version 3 to Enhance System-on-Chip (SoC) IP Assembly

8 April 2015

Arteris Delivers FlexNoC Version 3 to Enhance System-on-Chip (SoC) IP Assembly
PRWeb, Kurt Shuler

New version improves SoC designer productivity, provides foundation for future technologies

AppliedMicro Again Chooses Arteris FlexNoC for X-Gene Server on a Chip Products

31 March 2015

AppliedMicro Again Chooses Arteris FlexNoC for X-Gene Server on a Chip Products
PRWeb, Kurt Shuler

Shorter time-to-closure and end-to-end Quality-of-Service (QoS) tuning result in better interconnect performance for ARM-based server SoC

NoC løsning gør SoC design mere pålidelig [NoC solution enables more reliable SoC design]

27 March 2015

NoC løsning gør SoC design mere pålidelig [NoC solution enables more reliable SoC design]
Aktuel Elektronik (Denmark), Jorgen Sarlvit-Larsen

Californiske Arteris udvider sin network-on-chip teknologi med robust redundans, der gør det nemmere for chipdesignerne at udvikle fejltolerante SoC designs og opnå compliance med sikkerhedsstandarder

Focus More Attention On The SoC’s Central Nervous System

26 March 2015

Focus More Attention On The SoC’s Central Nervous System
Semiconductor Engineering (US), Kurt Shuler

The interconnect fabric is the backbone of any complex chip.

Rockchip Licenses Arteris FlexNoC Fabric IP for RK Series SoCs

18 March 2015

Rockchip Licenses Arteris FlexNoC Fabric IP for RK Series SoCs
PRWeb, Kurt Shuler

Network-on-chip interconnect IP provides strategic cost and time-to-market advantages to leading Chinese application processor vendor

Arteris Flexes Networking Muscle in TI’s Multi-standard IoT Chip

14 March 2015

Arteris Flexes Networking Muscle in TI’s Multi-standard IoT Chip
SemiWiki (US), Majeed Ahmad

Arteris Inc., a network-on-chip (NoC) interconnect IP solution provider, has joined hands with Texas Instruments Inc. to create an ultra-low-power chip that helps Internet of Things (IoT) devices go battery-less with energy harvesting and support coin cell-powered IoT operation for multiple years.

連結不同IP Arteris鎖定車用電子 [Arteris IP for automotive]

3 March 2015

連結不同IP Arteris鎖定車用電子 [Arteris IP for automotive]
Ctimes (Taiwan), C.Y. Yao

另外一家業者則相當的特別,該公司同樣與晶片開發有關,但這間公 司專職於協助不同IP之間的連結,名為Arteris,見長於NOC(Network On Chip 方案的開發與設計,成立於20023年。Arteris市場副總裁Kurt Shuler表示,目前如行動、車用與儲存等領域相關的主晶片供應商, 像是三星、高通、飛思卡爾與德州儀器等,都是其客戶群。

Streamlining Interconnect Integration Accelerates Globally Distributed Design

26 February 2015

Streamlining Interconnect Integration Accelerates Globally Distributed Design
Semiconductor Engineering (US), Kurt Shuler

Specialized teams find new ways to stitch individual efforts into the SoC fabric.

Partition Lines Growing Fuzzy

26 February 2015

Partition Lines Growing Fuzzy
Semiconductor Engineering (US), Ed Sperling

What used to be a straightforward progression from board to chipset to chip is no longer so obvious.

Custom Versus Platform Design

26 February 2015

Custom Versus Platform Design
Semiconductor Engineering (US), Ed Sperling

From automotive to consumer markets, strategies are all over the map when it comes to future design.

Arteris Sees Computational Consolidation Amid ADAS Gold Rush

25 February 2015

Arteris Sees Computational Consolidation Amid ADAS Gold Rush
SemiWiki (US), Majeed Ahmad

The sensor fusion in vehicles is leading to a new era of information sharing from almost all components of a car, including chassis, suspension and rapidly taking off Advanced Driver Assistance Systems (ADAS).

Arteris FlexNoC Helps Enable Texas Instruments Wireless Connectivity for the Internet of Things (IoT)

25 February 2015

Arteris FlexNoC Helps Enable Texas Instruments Wireless Connectivity for the Internet of Things (IoT)
PRWeb, Kurt Shuler

Network-on-chip interconnect enables complete family of industry’s lowest power RF devices for Zigbee® RF4CE™, Bluetooth® low energy and other IoT standards

Two Major Enterprise Solid State Disk (SSD) Vendors License Arteris FlexNoC Interconnect IP

18 February 2015

Two Major Enterprise Solid State Disk (SSD) Vendors License Arteris FlexNoC Interconnect IP
PRWeb, Kurt Shuler

New generation of enterprise SSD controllers to benefit from network-on-chip (NoC) data protection, high bandwidth PCI Express (PCIe)

Arteris Adds Functional Safety to NoC Interconnect IP, Aims Auto SoCs

17 February 2015

Arteris Adds Functional Safety to NoC Interconnect IP, Aims Auto SoCs
SemiWiki (US), Majeed Ahmad

Arteris Inc. has joined hands with Yogitech S.p.A. to help automotive system-on-chip (SoC) designers meet the required functional safety metrics and obtain the ISO 26262 certification for automotive safety integrity levels (ASIL) in the least possible time.

Sorry, IP Isn't EDA

17 February 2015

Sorry, IP Isn't EDA
EE Times (US), Charlie Janac

I overheard a conversation comparing the semiconductor IP business with the EDA business. At one point, they decided that "IP is EDA" because of the synergies between the two. While there are similarities, I beg to differ.

Arteris and YOGITECH Announce Strategic Partnership Enabling ISO 26262 Compliant Advanced Automotive Systems-on-Chip

17 February 2015

Arteris and YOGITECH Announce Strategic Partnership Enabling ISO 26262 Compliant Advanced Automotive Systems-on-Chip
PRWeb, Kurt Shuler

Integration of Arteris FlexNoC Resilience Package and YOGITECH faultRobust technology enables more efficient ISO 26262 and ASIL compliance

ArterisのCEOが語る:悪いけど、IPはEDAじゃないよ [Sorry, IP Isn't EDA]

17 February 2015

ArterisのCEOが語る:悪いけど、IPはEDAじゃないよ [Sorry, IP Isn't EDA]
EE Times Japan (Japan), Charlie Janac

半導体IPビジネスとEDAビジネスを比べている会話を耳にした。彼らは「IPはEDA」だという結論に達した。しかし、いくつかの関連性はあるものの、これらはまったく異なる代物だ。それぞれの分野で10年間を費やした私は、このことを学んだ。

Challenges For IC Security

5 February 2015

Challenges For IC Security
Semiconductor Engineering (US), Ernest Worthman

Who’s going to pay for it, and how is that going to impact power, performance, and the overall supply chain?

Moore's Law is Dead: Long Live SoC Designers

2 February 2015

Moore's Law is Dead: Long Live SoC Designers
Arteris Blog (US), Kurt Shuler

As the "Free Lunch" Era Closes, Chip Designers Grow in Value by Providing Innovative Ways to Increase Performance and Cut Power Consumption

First Look: 10nm

29 January 2015

First Look: 10nm
Semiconductor Engineering (US), Ed Sperling

Problems and an early look at best practices that will be required for dealing with the next level of complexity.

Automotive System Design Challenges

29 January 2015

Automotive System Design Challenges
Semiconductor Engineering (US), Ann Steffora Mutschler

New standards and complex ecosystem leaves companies scrambling to fit in.

The Top 35 ISO 26262 acronyms and abbreviations

5 January 2015

The Top 35 ISO 26262 acronyms and abbreviations
Arteris Blog (US), Kurt Shuler

A glossary of ISO 26262 abbreviations and acronyms can be a great help to understanding functional safety standards.

wire routing congestion presentation routing congestion technical papers routing congestion solved by network on chip interconnect for SoC