Efficiency: Separate NoC Transaction, Transport and Physical Layers
Typical interconnect solutions intermingle the transaction, transport and physical characteristics of the on-chip interconnect. This makes it difficult to deal with changes to the SoC once the interconnect is completed.
Comingling these layers also makes it difficult to efficiently implement advanced features like QoS, power domains, clock domains, and security.
the network, NIUs communicate with the attached IP cores via one of a number of standard IP sockets (interfaces), or through custom-built sockets developed by Arteris to meet specific customer needs.
Because most of the interconnect logic is resident in NIUs that are close to their respective IP blocks, there are fewer gates to place for the interconnect itself.
The Transport layer deals exclusively with packets. Only a limited amount of information in packet headers needs to be examined in order to determine the required transport operations. The Transport layer can safely ignore the specifics of the transactions being managed at its own level. This simplifies the hardware required for switching and routing functions, and enables higher operating frequencies.
In short, the interconnect topology is made of simple elements that operate independently without needing global control. Specific packet handling techniques guarantee quality of service or bandwidth. Optimization can be performed locally on specific routes, without affecting the NoC interconnect as a whole.
The Physical layer defines how packets are actually transmitted between NoC units. Various link types with different capabilities, such as transport links, globally asynchronous / locally synchronous (GALS) links for longer distances, or Chip-to-Chip links, can be employed.
Separate Transaction and Transport layers make it possible to change links, or their characteristics, without affecting the transport or transaction layers. Because all connections are point-to-point, high fan-out nets are prevented, thus providing better performance and easier routing.
Compared to other interconnects, Arteris technology requires fewer connections and wires, provides fully pipelinable units, and simplifies timing closure.
Arteris exceeded our expectations on the previous multi-core SoC platform, delivering exceptional performance and design efficiency. Arteris FlexNoC interconnect IP enables us to exceed our design frequency and power requirements while giving us more flexibility than possible using older interconnect technologies, like buses and crossbars.
Li Shiqin, IC Design Manager, Rockchip