Any Protocol, Any Architecture, Any Domain: The Most Flexible Interconnect
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| <<< Packetization and Serialization |
Arteris network on chip (NoC) technology is the most flexible interconnect technology because one can use any socket protocol, any architecture, and any combination of clock, voltage and power domains.
- AMBA AXI, OCP, or Any Protocols
- Distributed Architecture for Easier Routing
- Clock, Voltage and Power Management
- Security
AMBA AXI, OCP, or Any Socket Protocols
Arteris network on chip technology includes out-of-the-box support for AMBA AXI, AXI4, AHB, APB, and ACE-Lite protocols, in addition to other standards like OCP, PIF and BVCI.
With today’s platform based SoC design methodologies, it is important for design teams to be able to quickly generate derivatives based on a single SoC platform. These derivatives usually require changing IP blocks that use a different protocol configuration, or even an entirely different protocol, than the original IP blocks.
In traditional bus and crossbar interconnects, changing an IP block means not only dealing with a different transaction protocol, but also making changes to the path widths and physical bus topology to accommodate the new IP. At a minimum, bridging is usually required. In the worst case, changing IP blocks leads to back-end timing and physical placement issues that delay the release of what was promised as a “simple derivative.”
In comparison, changing an IP block on a NoC interconnect only requires changing the configuration of the network interface unit (NIU) to accommodate the protocol and bit width changes for that IP block. The NoC interconnect’s packet-based transport allows mixing data widths and clock rates.
Distributed Architecture for Easier Routing
Arteris NoC technology allows for easier back-end routing and timing convergence because, in addition to requiring fewer wires and fewer gates than traditional interconnects, the distributed architecture of interconnect elements like switches, FIFOs, and converters allows these elements to be automatically placed and routed in small physical areas distributed throughout the chip.
Protocol conversion, packetization and serialization are performed in the network interface units (NIU), which are physically located close to each NIU’s corresponding IP block and do not create placement and routing issues.
This is in direct contrast to a traditional bus or crossbar approach where the interconnect at the physical stage is a monolithic switch or series of switches that must be squeezed between existing IP blocks, along with the commensurate tangle of congested wires.
Clock, Voltage and Power Management
Today’s SoCs require advanced power management capabilities like dynamic voltage and frequency scaling (DVFS) to be competitive in power consumption and heat dissipation. Arteris NoC technology and graphical tools makes it easy to define and verify any number of independent clock, voltage and power domains in the interconnect to easily create complex power management schemes.
Dynamic Clock Gating is used so interconnect resources are only clocked when processing packets.
A versatile clock manager supports any clock and reset policy. Power domain partitioning is supported by power controller, power disconnect, and error handling IP within the interconnect. And voltage domains are automatically accommodated by automatically inserted asynchronous crossings and level shifter cells.
GALS technology (globally asynchronous/locally synchronous) is used for maximum clock domain management efficiency. Cross-clock boundaries are instantiated using small unidirectional bi-synchronous FIFOs, allowing for optimal latency with no handshake required. Clock boundaries can be partitioned along any link within the interconnect and the GALS elements can be bypassed for synchronous operation.
Power and voltage domains are separated by an electrical isolation layer, and individual IP blocks can be turned off using socket disconnect protocols. Retention registers are inserted when specific IP blocks must retain state when the power domain is shut off.
Power intent is captured and exported using the Common Power Format (CPF) and the Unified Power Format (UPF).
Security
SoC security schemes are highly proprietary yet must be developed and verified quickly. Arteris accommodates this need by providing extensible security firewall capabilities to allow the SoC designer to define how the interconnect responds to traffic which does not meet expected profiles.
These programmable firewalls within the network-on-chip interconnect protect IP blocks from unauthorized access and can be located anywhere in the interconnect.
All security features are programmable and customizable by the SoC architect for maximum security.
| <<< Separate Transaction, Transport and Physical Layers |
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