network on chip interconnect fabric for SoC

Enabling Technologies: Packetization and Variable Link Widths (Serialization)

The key to being able to reduce the number of wires in an interconnect consists of two enabling technologies: Packetization and Variable Link Widths (also known as “serialization”).

Encapsulating data in packets and and having the option to transport them serially are the two defining requirements for an interconnect technology to be considered a network on chip.

Contents:

 
<<< Separate Transaction, Transport and Physical Layers

Any Protocol, Any Architecture, Any Domain >>>

Packetization

zero latency noc for maximum bandwidth

With Arteris NoC technology, network interface units (NIU) manage communication with a connected IP core. NIUs convert traditional AMBA, OCP and proprietary protocol load and store transactions into packets for transport across the network. At the periphery of the network, NIUs communicate with the attached IP cores via one of a number of standard IP sockets (interfaces), or through custom-built sockets developed by Arteris to meet specific customer needs.

Because most of the interconnect logic is resident in NIUs that are close to their respective IP blocks, there are fewer gates to place for the interconnect itself.

Variable Link Widths (Serialization)

The transport layer deals exclusively with packets. Only a limited amount of information in packet headers needs to be examined in order to determine the required transport operations. The transport layer can safely ignore the specifics of the transactions being managed at its own level. This simplifies the hardware required for switching and routing functions, and enables higher operating frequencies.

In short, the interconnect topology is made of simple elements that operate independently without needing global control. Specific packet handling techniques guarantee quality of service or bandwidth. Optimization can be performed locally on specific routes, without affecting the NoC interconnect as a whole.

Benefits of Narrower Link Widths

Compared to other interconnects, Arteris technology requires fewer connections and wires, provides fully pipelinable units, and simplifies timing closure.

The physical layer defines how packets are actually transmitted between NoC units. Various link types with different capabilities, such as transport links, globally asynchronous / locally synchronous (GALS) links for longer distances, or Chip-to-Chip links, can be employed.

Separate transaction and transport layers make it possible to change links, or their characteristics, without affecting the transport or transaction layers. Because all connections are point-to-point, high-fanout nets are prevented, thus providing better performance and easier routing.

<<< Separate Transaction, Transport and Physical Layers

Any Protocol, Any Architecture, Any Domain >>>


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Springer Verlag Journal Design Automation for Embedded Systems peer reviewed article by Arteris routing congestion solved by network on chip interconnect for SoC wire routing congestion presentation network on chip interconnect helps system on chip economics, reduces cost, increases revenues