Arteris: The Network-on-Chip Company, corporate web sub-banner
Back to Press Releases

Arteris Delivers Major Productivity Features for its Network-On-Chip Interconnect IP and Toolset

NoC pioneer’s seventh major production release includes advanced memory traffic support, System Verilog-based verification tool and multi-voltage support

San Jose, California – October 22, 2008 – Arteris Inc., the leading Network-on-Chip (NoC) solutions provider today announced that the latest release of its Arteris NoC Solution is available for immediate delivery. The newest version of the Arteris NoC Solution represents a major advance in Network-on-Chip Interconnect IP technology. The release contains the following key new features:

  1. Advanced Memory Traffic Support. Memory interleaving support allows a set of memory controllers and associated memory chips to appear as a single interconnect target. Memory accesses are balanced between the controllers, transparently to the software, which view the entire memory space as a single region. This feature is particularly important for advanced multi-media designs that must quickly handle large capacity of multi-media data traffic such as High Definition Set Top Boxes and Digital Television SoCs.
  2. Guaranteed Bandwidth Quality of Service. Leveraging the already patented pressure-based Quality of Service (QoS) policy of the Arteris NoC, the new bandwidth regulator component of the NoC IP library provides an initiator IP or group of initiator IPs a guaranteed minimum bandwidth to a shared target, still allowing unused allocated bandwidth to be redistributed to any initiator that might require it. The software programmability of this IP makes it configurable in order to adapt to variety of system applications. With this new feature, the Arteris NoC solution provides a complete functionality in terms of Quality of Service support – for digital television, set top box, wireless or automotive SoCs.
  3. Automated NoC Instance Verification. NoCverifierTM tool for automatic verification of customer-developed NoC Instances based on System Verilog. This design tool provides exhaustive automatic protocol coverage for all routes in the NoC, whatever initiator and target standard are (OCP, AXI, AHB, APB). Specific tests have also been developed by Arteris to check for power domain activation, performance monitoring and NoC debug subsystems. NoCverifier can be also used to verify, non-Arteris interconnects, decreasing SoC time to market.
  4. Performance monitoring. Customers can now easily analyze on-chip data traffic performance by using their NoC Interconnects as logic analyzers on a chip. The Arteris statistic collector allows embedded application software developers to analyze SoC behavior and measure in situ performances (on FPGA or silicon), in order to analyze and tune application and SoC drivers software for maximum performance.
  5. Security Interface. Embedding of customer proprietary hardware security IP is supported, allowing complete confidentiality of proprietary hardware security schemes and leading to more secure electronic products.
  6. Voltage domains. In addition to independent power domain support, allowing parts of the NoC to be turned off according to application requirements, NoC instances can also be split into several voltage domains. This allows a dynamic tuning of the voltage and clock rate of parts of the NoC to actual application computing power requirement, as part of a global SoC fixed or dynamic (DFVS) multi-voltage strategy.

About Arteris

Arteris, Inc. provides Network-on-Chip (NoC) interconnect IP, NoC generation and verification tools to improve performance of system-on-chip (SoC) architectures for multimedia, mobile, telecom, and other applications. Arteris' NoC solution allows chip developers to implement scalable, efficient and high-performance SoC designs, overcoming limitations of traditional layered or pipelined bus-based architectures. Results obtained by using Arteris NoC Solution include lower power, higher performance, lower risk of development and faster delivery of complex SoCs while increasing profits.

Founded by networking experts, Arteris operates globally with headquarters in San Jose, California and an engineering center in Paris, France. Arteris is a private company backed by a group of international investors including TVM Capital, Crescendo Ventures, Ventech, Synopsys and DoCoMo Capital . More information can be found at www.arteris.com

For more Arteris information, contact:
K. Charles Janac
Arteris, Inc.
+1 408-625-6001
Charlie.janac@arteris.com

Mike Sottak
Wired Island, Ltd.
+1 408-876-4418
mike@wiredislandpr.com

Arteris, NoCverifier and the Arteris logo are trademarks of Arteris. All other trademarks or registered trademarks are the property of their respective owners.

###

wire routing congestion presentation routing congestion technical papers routing congestion solved by network on chip interconnect for SoC