Arteris Press Releases

Arteris FlexNoC IP and FlexNoC Resilience Package Licensed by Dream Chip Technologies for ADAS SoC

NoC interconnect fabric IP to be on-chip communications backbone of European Commision-funded automated driver assistance system (ADAS) project

CAMPBELL, California — May 31, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that Dream Chip Technologies GmbH has licensed Arteris FlexNoC interconnect IP with the Arteris FlexNoC Resilience Package for use in the European Commission / ENIAC THINGS2DO automotive advanced driver assistance systems (ADAS) reference development platform project.

The competing goals of creating a highly complex ADAS SoC with functional safety requirements while reducing Tier-1 TTM motivated us to choose Arteris FlexNoC over other interconnects. The Arteris NoC technology reduces wire routing congestion and QoS issues while allowing us to more easily implement the data protection features required for ADAS systems to meet higher levels of ISO 26262 ASIL certification.


Dr.-Ing. Jens Benndorf, Managing Director and COODream Chip Technologies

Topics: automotive semiconductors Arteris FlexNoC new customer flexnoc resilience package ADAS iso 26262 ASIL

Arteris Ncore Cache Coherent Interconnect IP enabled by ARM’s Cycle Models

Cycle-accurate SystemC models power highly scalable verification and performance optimization infrastructure

CAMPBELL, California — May 24, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that it has used ARM® Cycle Models for use in hardware and performance verification Ncore™ Cache Coherent Interconnect IP.

ARM Cycle Models provide early, secure access to ARM’s leading edge IP. Enabling Arteris to integrate this technology into their development infrastructure highlights ARM’s commitment to enabling design optimization, time-to-market and cost-efficiency gains for our ecosystem partners.


Javier Orensanz, General Manager, Development Solutions GroupARM

Topics: ARM new product AMBA ACE protocol cache coherent IP ARM cycle models Ncore cycle accurate simulation heterogeneous cache coherency cache coherency cache coherent interconnect system level modeling

Arteris Unveils Ncore Cache Coherent Interconnect for Efficient Heterogeneous Multicore SoC Designs

Configurable, scalable and distributed architecture allows optimal system performance, power consumption and cost while easing timing closure

CAMPBELL, California — May 24, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced Ncore™ cache coherent interconnect IP version 1.5. Ncore IP is a distributed heterogeneous cache coherent interconnect that allows system architects to efficiently design fully-coherent systems with the advantages of multiple configurable snoop filters and embedded caches, providing greater flexibility than fixed or centralized cache coherency interconnects typically found in today’s SoC designs.

We chose Ncore interconnect IP because of its outstanding configurability and flexibility, allowing us to create highly differentiated cache coherent SoCs using processors and accelerator IP optimized for the application.


Benny Chang, Vice President of R&D, Automotive MCU and Processors Business LineNXP Semiconductors

Topics: new product cache coherent IP Ncore heterogeneous cache coherency cache coherency cache coherent interconnect

Arteris Ncore Cache Coherent Interconnect IP is Implemented by NXP

Cache coherent IP combined with resilience features enables functional safety for heterogeneous cache coherent systems-on-chip (SoC)

CAMPBELL, California — May 24, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that NXP Semiconductors has licensed Ncore™ cache coherent interconnect IP for use in its SoCs.

We chose Ncore interconnect IP because of its outstanding configurability and flexibility, allowing us to create highly differentiated cache coherent SoCs using processors and accelerator IP optimized for the application. Having precise control over the configuration of coherent agent ports, memory interfaces, and snoop filters helps us make more power- and area-efficient SoCs. The distributed hardware architecture allows for a more efficient physical design by easing back-end placement and timing closure.


Benny Chang, Vice President of R&D, Automotive MCU and Processors Business LineNXP Semiconductors

Topics: new customer new product automotive cache coherent IP Ncore heterogeneous cache coherency cache coherency cache coherent interconnect NXP Semiconductors

Arteris Redefines Heterogeneous Multicore Cache Coherency with Configurable, Distributed Semiconductor Architecture

Technology increases area and power efficiency of systems built with semiconductor IP from multiple sources

CAMPBELL, California — May 17, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today introduced a semiconductor design technology that enhances the ability of SoC architects to create efficient cache-coherent systems with IP sourced from multiple vendors. Allowing the industry’s first distributed heterogeneous cache-coherent interconnect, the new technology helps designers achieve higher frequency, lower power consumption and reduced time-to-market in producing differentiated SoCs that span multiple design domains such as mobility, HDTV, enterprise storage, automotive advanced driver assistance systems (ADAS), micro-server and networking markets.

The exploding cost of the latest semiconductor process nodes is forcing design teams to evaluate new architectural approaches for SoC design. The distributed cache coherent architecture that Arteris offers will help system designers better utilize the processing resources in the SoC, making computing throughput more efficient.


Linley Gwennap, Principal AnalystThe Linley Group

Topics: new product cache coherent IP heterogeneous cache coherency cache coherency cache coherent interconnect