Configurable, scalable and distributed architecture allows optimal system performance, power consumption and cost while easing timing closure
CAMPBELL, California — May 24, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced Ncore™ cache coherent interconnect IP version 1.5. Ncore IP is a distributed heterogeneous cache coherent interconnect that allows system architects to efficiently design fully-coherent systems with the advantages of multiple configurable snoop filters and embedded caches, providing greater flexibility than fixed or centralized cache coherency interconnects typically found in today’s SoC designs.
We chose Ncore interconnect IP because of its outstanding configurability and flexibility, allowing us to create highly differentiated cache coherent SoCs using processors and accelerator IP optimized for the application.
Benny Chang, Vice President of R&D, Automotive MCU and Processors Business Line, NXP Semiconductors
Ncore interconnect IP enhances SoC design configurability by simultaneously enabling different coherent protocol implementations, cache state models and cache organizations. This enables the creation of heterogeneous cache coherent SoCs for fast-moving markets like wireless mobility, HDTV, enterprise storage, automotive advanced driver assistance systems (ADAS), micro-servers and networking.
Version 1.5 of the Ncore interconnect IP enables from one to eight fully coherent agent ports, multiple snoop filters with configurable sizes and agent associativity, and configurable embedded proxy caches (also called “I/O caches”). The architectural limits of Ncore extend far beyond the version 1.5 feature set, allowing a robust roadmap of future Ncore products.
Arteris Ncore IP incorporates configurable proxy caches to increase the performance of non-coherent agents accessing the coherent subsystem, allowing non-cached IP to achieve the benefits of system-wide coherency. Ncore is extremely configurable, enabling designers to select the number of coherent agent and memory interface ports, number and sizes of configurable snoop filters, and number and sizes of embedded proxy caches.
In contrast to fixed or hub-based cache controller implementations, the Ncore interconnect is a distributed solution consisting of replicated units and core components, allowing the interconnect IP to scale to fit a variety of processing requirements. Distributing a hardware architecture in this manner also eases power management, physical implementation and timing closure.
- Heterogeneous Coherent Agents - Allows simultaneous use of different coherent protocol implementations, cache state models and cache organizations, enabling use of coherent IP from multiple vendors and internal development teams.
- Distributed Architecture – Eases floor planning and timing closure while enabling the industry’s most flexible clock and power management.
- Configurable Snoop Filters – Configure the organization, size and association for multiple individual snoop filters based on caching agent characteristics in the system.
- Proxy Caches – Enable legacy IP to achieve the benefits of system-wide coherency.
- Scalability – Componentized solution allows efficient scaling to match system requirements.
“We’ve developed Ncore specifically to provide system architects with the increased flexibility and configurability required to efficiently meet application-specific performance goals for the most demanding systems,” said K. Charles Janac, President and CEO of Arteris. “The goal of our Ncore interconnect is to facilitate greater use of cache coherency in the semiconductor industry by enabling accelerators, such as video and imaging processors, to be made coherent with the main central processing units (CPUs).”
Ncore version 1.5 is the third release of the Ncore cache coherent interconnect IP solution and is available immediately.
“We chose Ncore interconnect IP because of its outstanding configurability and flexibility, allowing us to create highly differentiated cache coherent SoCs using processors and accelerator IP optimized for the application,” said Benny Chang, Vice President of R&D for NXP’s Automotive MCU and Processors Business Line. “Having precise control over the configuration of coherent agent ports, memory interfaces, and snoop filters helps us make more power- and area-efficient SoCs. The distributed hardware architecture allows for a more efficient physical design by easing back-end placement and timing closure.”
“The ARM ecosystem continues to deliver energy-efficient solutions across a variety of performance points, ensuring greater integration and faster time to market,” said Charlene Marini, vice president, segment marketing, ARM. “Working with valued partners like Arteris and the wider community delivers a diverse range of SoC building blocks that implement ARM® AMBA® technology. These collaborations will further drive innovation in heterogeneous cache coherent systems.”
“Optimizing heterogeneous multicore SoC designs requires a configurable and flexible interconnect,” said John Koeter, vice president of marketing for IP and prototyping at Synopsys. “The integration of Arteris’ Ncore IP with Synopsys’ prototyping and verification solutions enables system designers to analyze architecture performance and power earlier and verify subsystem performance is met during implementation.”
Arteris, Inc. provides system-on-chip (SoC) interconnect IP and tools to accelerate SoC semiconductor assembly for a wide range of applications. Rapid semiconductor designer adoption by customers such as Samsung, Huawei / Hisilicon, Mobileye, Altera, and Texas Instruments has resulted in Arteris being the only semiconductor IP company to be ranked in the Inc. 500 and Deloitte Technology Fast 500 lists in 2012 and 2013. Customer results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. More information can be found at www.arteris.com.
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