AI HARDWARE & EDGE AI SUMMIT 2023

Arteris – Accelerating SoC Creation and Integration

From semiconductor manufacturers to OEMs, hyperscale system houses to semiconductor design houses, the world’s most transformative companies rely on Arteris interconnect IP and SoC integration technology to speed time to market, reduce risk, optimize product performance, maximize team productivity, and lower overall total costs.

With over 3+ Billion SoCs shipped in electronic systems and 700+ SoC design starts, Arteris is the industry leader with proven technology and expert support.

Join Session - The Development of the RISC-V Ecosystem for AI

Topic: The Development of the RISC-V Ecosystem for AI
When: Tuesday, September 12th at 6:10pm
Moderator: Sally Ward-Foxton, Senior Reporter, EETimes
Panelists
: Laurent Moll, Chief Operating Officer, Arteris; Jim Keller, CEO, Tenstorrent; Raja Koduri, Board Member, Tenstorrent; Bing Yu, Senior Techinical Director, Andes Technology

Explore Products

FlexNoC Interconnect IP

Create physically valid NoCs faster

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 XL option icon

FlexNoC XL Option

Enhanced scalability and flexibility to support AI and ML chip designs

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 FuSa option icon

FlexNoC FuSa Option

ISO 26262 and IEC 61508 compliance and improved enterprise SSD endurance

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Ncore Interconnect IP

Solve multi-core design challenges with safety support

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CodaCache Last-Level Cache IP

Fast local memory for high-performance systems

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Magillem Connectivity

Automate SoC assembly to eliminate tedious tasks

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Magillem Registers

Enable effective hardware/software interface development for schedule acceleration

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CSRCompiler

Streamline hardware/software interface foundation creation

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Read Case Studies

Inuitive a new iteration of an existing vision-on-chip device quickly and easily, meeting an aggressively short time-to-market schedule using Arteris interconnect IP.

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SiMa.ai designed a state-of-the-art machine learning accelerator (MLA) and they needed an easy way to generate a NoC quickly. Using Arteris IP, they saved years on their project timeline.

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Sondrel delivered implementation-ready RTL based on client concepts on advanced ADAS SoC designs in record time. They reduce design time from 4-5 months down to 1-2 months using Arteris IP.

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