Arteris Press Releases

Arteris Joins CCIX Consortium to Support Heterogeneous Cache Coherency Deployment

Interconnect IP pioneer offers technology extending cache coherence to on-chip and off-chip hardware accelerators and processors

CAMPBELL, Calif. — Oct. 11, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that it has joined the Cache Coherent Interconnect for Accelerators Consortium, also known as the CCIX Consortium.

Our expertise in supporting the leading industry cache coherent protocols allows Arteris to accelerate the development and deployment of highly scalable CCIX-based solutions in the data center. Our Ncore cache coherent interconnect IP is our first product to leverage this foundational technology, and CCIX-based systems will provide even more opportunities for this technology to proliferate.


Kurt Shuler, Vice President, Marketing, Arteris

Topics: arteris partner Ncore CCIX

ARM and Arteris Extend Partnership to Deliver Additional Interconnect Options to SoC Designers

Arteris access to ARM® Cortex®-A15 and ARM Cortex-A7 microprocessor cores to enhance the success and diversity of ARM technology in mobility and consumer SoCs

SUNNYVALE, California — April 17, 2013 — Arteris and ARM (LON: ARM; Nasdaq: ARMH) have signed a multi-year agreement that expands Arteris’ access to ARM processor core IP. The two companies have broadened their cooperation to aid the development of future Arteris coherent interconnect IP products that more closely integrate with Arteris’ pioneering FlexNoC® network-on-chip technology and ARM’s processor IP.

We are enabling additional interconnect options to support the rapid adoption of ARM technology. These new options will help ARM and Arteris customers build new interconnect architectures. This is another step forward for the ARM community and for Arteris, which was a participant in the ARM AMBA® 4 ACE™ specification process.


Noel Hurley, Vice President of Marketing and Strategy, Processor Division, ARM

Topics: ARM AMBA ACE protocol cache coherent IP arteris partner