Arteris Press Releases

Arteris IP FlexNoC® Interconnect Licensed by Baidu for Kunlun AI Cloud Chips for Data Center

NoC interconnect IP optimizes dataflow for revolutionary Cloud-To-Edge artificial intelligence (AI) system-on-chip (SoC) architecture

CAMPBELL, Calif. – January 15, 2019 – Arteris IP, the leading supplier of innovative, silicon-proven network-on-chip(NoC) interconnect intellectual property, today announced that Baidu has licensed Arteris IP FlexNoC Interconnect for use in its high-performance Kunlun AI cloud chip for data center.

The Arteris FlexNoC interconnect IP helps us greatly by enabling not only high bandwidth on-chip communications but also load-balanced data traffic to off-chip memory, all while simplifying our backend timing closure. In addition, Arteris IP’s strong local support team has been a trusted partner in our AI chip development projects.


Jian Ouyang, Principal ArchitectBaidu

Topics: new customer china machine learning artificial intelligence neural network AI chips training chips flexnoc ai package Baidu

Arteris IP Announces New FlexNoC® 4 Interconnect IP with Artificial Intelligence (AI) Package

Industry leading commercial interconnect IP accelerates development of next-generation deep neural network (DNN) and machine learning systems

CAMPBELL, Calif. – October 31, 2018 – Arteris IP, the world’s leading supplier of silicon-proven commercial network-on-chip (NoC) interconnect intellectual property (IP)today announced the new Arteris IP FlexNoC version 4 interconnect IP and the companion AI Package. FlexNoC 4 and the AI Package (“FlexNoC 4 AI”) implement many new technologies that ease the development of today’s most complex AI, deep neural network (DNN), and autonomous driving systems-on-chip (SoC).

Numerous startups are attempting to develop SoCs for neural-network training and inference, but to be successful, they must have the interconnect IP and tools required to integrate such complex, massively parallel processors while meeting the requirements for high-bandwidth on-chip and off-chip communications. Arteris IP has the experience and interconnect IP to help these companies succeed, and FlexNoC 4 with the AI Package provides the features required for AI chips in an easy-to-use and highly configurable form.


Mike Demler, Senior Analyst and Senior EditorThe Linley Group & Microprocessor Report

Topics: SoC design new product machine learning artificial intelligence neural network QoS AI chips training chips noc multicast ring noc flexnoc ai package mesh noc torus noc

Arteris FlexNoC® Licensed by Canaan Creative for Artificial Intelligence ASICs

Semiconductor interconnect IP enables power-efficient processing in semi-autonomous aerial imaging devices

CAMPBELL, Calif. — May 1, 2018 — Arteris IP, the innovative supplier of silicon-proven commercial network-on-chip (NoC) interconnect intellectual property, today announced that Canaan Creative Co., Ltd., has licensed Arteris FlexNoC interconnect IP as the on-chip communications backbone of their next generation artificial intelligence (AI) ASIC.

Topics: Arteris FlexNoC new customer china artificial intelligence AI Canaan Creative

Arteris IP and Synopsys Accelerate the Optimization of Heterogeneous Multicore Neural Network Systems-on-Chip

Ncore Cache Coherent Interconnect IP and Synopsys Platform Architect fast-tracks integration for autonomous driving and artificial intelligence (AI) markets

CAMPBELL, Calif. — January 30, 2018 — Arteris IP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced the integration of its Ncore Cache Coherent IP with the Synopsys® Platform Architect™ virtual prototyping solution to provide designers of neural network and autonomous driving SoCs with the ability to analyze system-level performance and power consumption earlier in the design cycle for their next-generation multicore architectures.

Combining Platform Architect and Ncore System models provides designers with the ability to analyze and optimize an entire heterogeneous multicore SoC architecture before RTL is available.


Eshel Haritan, Vice President of R&D, Verification Group, Synopsys

Topics: Synopsys Ncore artificial intelligence neural network Platform Architect SystemC ncore cache coherent interconnect