Arteris Press Releases

ArterisIP Ncore Cache Coherent Interconnect and Resilience Package Licensed by NXP

CAMPBELL, Calif. — September 19, 2017 — ArterisIP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that NXP Semiconductors has licensed additional uses of Ncore Cache Coherent Interconnect IP and Ncore Resilience Packages.

We had an excellent experience implementing ArterisIP’s Ncore Cache Coherent Interconnect IP in our previous SoC developments so we have chosen to expand the adoption of this technology for our next generation SoCs.


Benny Chang, Vice President of R&D, Automotive MCU and Processors Business LineNXP Semiconductors

Topics: new customer automotive Ncore heterogeneous cache coherency cache coherent interconnect NXP Semiconductors automotive functional safety ncore resilience package ISO 26262 ASIL D autonomous driving

Arteris Ncore Cache Coherent Interconnect IP enabled by ARM’s Cycle Models

Cycle-accurate SystemC models power highly scalable verification and performance optimization infrastructure

CAMPBELL, California — May 24, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that it has used ARM® Cycle Models for use in hardware and performance verification Ncore™ Cache Coherent Interconnect IP.

ARM Cycle Models provide early, secure access to ARM’s leading edge IP. Enabling Arteris to integrate this technology into their development infrastructure highlights ARM’s commitment to enabling design optimization, time-to-market and cost-efficiency gains for our ecosystem partners.


Javier Orensanz, General Manager, Development Solutions GroupARM

Topics: ARM new product AMBA ACE protocol cache coherent IP ARM cycle models Ncore cycle accurate simulation heterogeneous cache coherency cache coherency cache coherent interconnect system level modeling

Arteris Unveils Ncore Cache Coherent Interconnect for Efficient Heterogeneous Multicore SoC Designs

Configurable, scalable and distributed architecture allows optimal system performance, power consumption and cost while easing timing closure

CAMPBELL, California — May 24, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced Ncore™ cache coherent interconnect IP version 1.5. Ncore IP is a distributed heterogeneous cache coherent interconnect that allows system architects to efficiently design fully-coherent systems with the advantages of multiple configurable snoop filters and embedded caches, providing greater flexibility than fixed or centralized cache coherency interconnects typically found in today’s SoC designs.

We chose Ncore interconnect IP because of its outstanding configurability and flexibility, allowing us to create highly differentiated cache coherent SoCs using processors and accelerator IP optimized for the application.


Benny Chang, Vice President of R&D, Automotive MCU and Processors Business LineNXP Semiconductors

Topics: new product cache coherent IP Ncore heterogeneous cache coherency cache coherency cache coherent interconnect

Arteris Ncore Cache Coherent Interconnect IP is Implemented by NXP

Cache coherent IP combined with resilience features enables functional safety for heterogeneous cache coherent systems-on-chip (SoC)

CAMPBELL, California — May 24, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that NXP Semiconductors has licensed Ncore™ cache coherent interconnect IP for use in its SoCs.

We chose Ncore interconnect IP because of its outstanding configurability and flexibility, allowing us to create highly differentiated cache coherent SoCs using processors and accelerator IP optimized for the application. Having precise control over the configuration of coherent agent ports, memory interfaces, and snoop filters helps us make more power- and area-efficient SoCs. The distributed hardware architecture allows for a more efficient physical design by easing back-end placement and timing closure.


Benny Chang, Vice President of R&D, Automotive MCU and Processors Business LineNXP Semiconductors

Topics: new customer new product automotive cache coherent IP Ncore heterogeneous cache coherency cache coherency cache coherent interconnect NXP Semiconductors