Arteris Press Releases

Arteris Ncore Cache Coherent Interconnect IP Licensed by Toshiba Corporation (Toshiba) for Automotive ADAS

Heterogeneous cache coherency and simpler ISO 26262 automotive functional safety qualification enabled by configurable interconnect IP

CAMPBELL, Calif. — Nov. 1, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that Toshiba has licensed Arteris Ncore Cache Coherent Interconnect IP for use in its image recognition processors for ADAS applications.

In evaluating cache coherent interconnects, we found that Arteris Ncore was the interconnect that provided us with the flexibility to fully optimize our system while also providing the data protection features we require to meet the highest possible ISO 26262 requirements. Arteris Ncore IP is a key component of our image recognition processor architecture.


Nobuaki Otsuka, Senior Manager, Mixed Signal IC Design Department, Toshiba

Topics: ISO 26262 automotive semiconductors new customer new product japan flexnoc resilience package ADAS Ncore cache coherent interconnect advanced driver assistance systems adas imaging processor

Arteris Joins CCIX Consortium to Support Heterogeneous Cache Coherency Deployment

Interconnect IP pioneer offers technology extending cache coherence to on-chip and off-chip hardware accelerators and processors

CAMPBELL, Calif. — Oct. 11, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that it has joined the Cache Coherent Interconnect for Accelerators Consortium, also known as the CCIX Consortium.

Our expertise in supporting the leading industry cache coherent protocols allows Arteris to accelerate the development and deployment of highly scalable CCIX-based solutions in the data center. Our Ncore cache coherent interconnect IP is our first product to leverage this foundational technology, and CCIX-based systems will provide even more opportunities for this technology to proliferate.


Kurt Shuler, Vice President, Marketing, Arteris

Topics: arteris partner Ncore CCIX

Arteris Ncore Cache Coherent Interconnect IP enabled by ARM’s Cycle Models

Cycle-accurate SystemC models power highly scalable verification and performance optimization infrastructure

CAMPBELL, California — May 24, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that it has used ARM® Cycle Models for use in hardware and performance verification Ncore™ Cache Coherent Interconnect IP.

ARM Cycle Models provide early, secure access to ARM’s leading edge IP. Enabling Arteris to integrate this technology into their development infrastructure highlights ARM’s commitment to enabling design optimization, time-to-market and cost-efficiency gains for our ecosystem partners.


Javier Orensanz, General Manager, Development Solutions GroupARM

Topics: ARM new product AMBA ACE protocol cache coherent IP ARM cycle models Ncore cycle accurate simulation heterogeneous cache coherency cache coherency cache coherent interconnect system level modeling

Arteris Unveils Ncore Cache Coherent Interconnect for Efficient Heterogeneous Multicore SoC Designs

Configurable, scalable and distributed architecture allows optimal system performance, power consumption and cost while easing timing closure

CAMPBELL, California — May 24, 2016 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced Ncore™ cache coherent interconnect IP version 1.5. Ncore IP is a distributed heterogeneous cache coherent interconnect that allows system architects to efficiently design fully-coherent systems with the advantages of multiple configurable snoop filters and embedded caches, providing greater flexibility than fixed or centralized cache coherency interconnects typically found in today’s SoC designs.

We chose Ncore interconnect IP because of its outstanding configurability and flexibility, allowing us to create highly differentiated cache coherent SoCs using processors and accelerator IP optimized for the application.


Benny Chang, Vice President of R&D, Automotive MCU and Processors Business LineNXP Semiconductors

Topics: new product cache coherent IP Ncore heterogeneous cache coherency cache coherency cache coherent interconnect