Arteris Press Releases

Arteris IP Ncore® and FlexNoC® Interconnects and Resilience Packages Licensed by Mobileye for AI-Powered EyeQ Chips

Next generation ASIL B(D) autonomous driving systems to be enabled by ISO 26262-compliant cache coherent and non-coherent interconnect IP

CAMPBELL, Calif. — July 10, 2018 — Arteris IP, the leading supplier of innovative, silicon-proven network-on-chip(NoC) interconnect intellectual property, today announced that Mobileye has purchased multiple licenses of Arteris IP Ncore Cache Coherent Interconnect, FlexNoC Interconnect, and the Ncore and FlexNoC Resilience Packages for functional safety and artificial intelligence (AI) hardware acceleration. This broad portfolio of Arteris IP interconnect technology will be the on-chip communications backbone of Mobileye’s next-generation ISO 26262 ASIL B(D) capable next generation EyeQ system-on-chip (SoC) devices.

We chose the Arteris Ncore cache coherent interconnect because of its unique proxy caches and their ability to underpin high-performance, low power, cache coherent clusters of our unique AI accelerators. And with our prior experience using FlexNoC and the FlexNoC Resilience Packages for functional safety, we trust Arteris IP to be the highest performing and safest choice for ISO 26262-compliant NoC IP.”


Elchanan Rushinek, Vice President of EngineeringMobileye

Topics: mobileye ncore resilience package ncore cache coherent interconnect flexnoc interconnect flexnoc resilience package eyeq iso 26262 ASIL new customer

Arteris IP and Synopsys Accelerate the Optimization of Heterogeneous Multicore Neural Network Systems-on-Chip

Ncore Cache Coherent Interconnect IP and Synopsys Platform Architect fast-tracks integration for autonomous driving and artificial intelligence (AI) markets

CAMPBELL, Calif. — January 30, 2018 — Arteris IP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced the integration of its Ncore Cache Coherent IP with the Synopsys® Platform Architect™ virtual prototyping solution to provide designers of neural network and autonomous driving SoCs with the ability to analyze system-level performance and power consumption earlier in the design cycle for their next-generation multicore architectures.

Combining Platform Architect and Ncore System models provides designers with the ability to analyze and optimize an entire heterogeneous multicore SoC architecture before RTL is available.


Eshel Haritan, Vice President of R&D, Verification Group, Synopsys

Topics: Ncore Synopsys Platform Architect SystemC neural network artificial intelligence ncore cache coherent interconnect