Arteris Press Releases

Arteris IP and Magillem Partner to Create Integrated System-on-Chip Architecture Environment

Single environment allows design teams to more easily build AI and autonomous driving SoCs using FlexNoC and Ncore IP and share data for ISO 26262 compliance

CAMPBELL, Calif. — June 25, 2018 — Arteris IP, the world’s leading supplier of silicon-proven commercial network-on-chip (NoC) interconnect intellectual property (IP), and Magillem, the leading provider of front-end design XML solutions and best-in-class tools to reduce the global cost of complex designs, today announced a partnership and product integration that accelerates the architectural definition of complex chips.

The Magillem integration with Arteris FlexNoC and Ncore interconnect IP enables not only the easier design of highly complex systems-on-chip, but also more efficient and automated information sharing between IP providers, semiconductor vendors, ISMs and systems houses.”


Isabelle Geday, CEOMagillem

Topics: new product XML arteris ip partner ip-xact magillem

Arteris IP Announces CodaCache™️ Standalone Last Level Cache

Unlock the full performance of your SoC architecture with a last level cache

CAMPBELL, Calif. — June 7, 2018 — Arteris IP, the leading supplier of innovative, silicon-proven network-on-chip(NoC) interconnect intellectual property, today announced the CodaCache standalone last level cache (LLC) for high-performance systems-on-chip (SoCs).

Designers will be attracted to the variety of use cases that CodaCache IP supports, including dedicated, shared, and distributed partitioning, as well as its use as on-chip scratchpad storage.”


Mike Demler, Senior Analyst and Senior EditorThe Linley Group and  Microprocessor Report

Topics: new product CodaCache

ArterisIP announces Ncore 3 Cache Coherent Interconnect

Enables next-generation machine learning and autonomous driving SoCs with support for Arm AMBA CHI protocol, CCIX, and ISO 26262 Functional Safety

Linley Processor Conference 2017, SANTA CLARA, Calif. — October 4, 2017 — ArterisIP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced the Ncore Cache Coherent Interconnect IP version 3 along with the optional Ncore Resilience Package for functional safety.

As current users of the Ncore cache coherent interconnect, we are excited about the technical innovation in ArterisIP’s new Ncore 3 IP. Enabling both the AMBA CHI and ACE protocols in the same SoC will allow for greater use of existing IP in high-performance systems.


Mr. Yu Li, Vice President , ZTE (SaneChips)

Topics: new product AMBA ACE protocol Ncore cache coherent interconnect CCIX ncore resilience package ISO 26262 certification AMBA5 CHI

ArterisIP Advances Machine Learning SoC Design with Ncore 2.0 Cache Coherent Interconnect and Resilience Package

SoC interconnect IP enables highly scalable neural network systems with integrated hardware functional safety features for ISO 26262 ASIL D compliance

Linley Autonomous Hardware Conference 2017, SANTA CLARA, Calif. — April 6, 2017 — ArterisIP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced the Ncore 2.0 Cache Coherent Interconnect IP and the optional Ncore Resilience Package to accelerate and enhance the creation of next-generation designs for autonomous driving systems and advanced driver assistance systems (ADAS).

We are very impressed with the new ArterisIP Ncore interconnect IP technologyArterisIP Ncore 2.0 interconnect IP offers even higher scalability along with the Coherent Memory Cache, which reduces DRAM accesses while maintaining area efficiency.


Mr. Yu Li, Vice President, Sanechips (Subsidiary of ZTE)

Topics: ISO 26262 new product machine learning Ncore automotive functional safety ArterisIP ncore resilience package neural networks