Arteris Press Releases

ArterisIP Advances Machine Learning SoC Design with Ncore 2.0 Cache Coherent Interconnect and Resilience Package

SoC interconnect IP enables highly scalable neural network systems with integrated hardware functional safety features for ISO 26262 ASIL D compliance

Linley Autonomous Hardware Conference 2017, SANTA CLARA, Calif. — April 6, 2017 — ArterisIP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced the Ncore 2.0 Cache Coherent Interconnect IP and the optional Ncore Resilience Package to accelerate and enhance the creation of next-generation designs for autonomous driving systems and advanced driver assistance systems (ADAS).

We are very impressed with the new ArterisIP Ncore interconnect IP technologyArterisIP Ncore 2.0 interconnect IP offers even higher scalability along with the Coherent Memory Cache, which reduces DRAM accesses while maintaining area efficiency.


Mr. Yu Li, Vice President, Sanechips (Subsidiary of ZTE)

Topics: ISO 26262 new product machine learning Ncore automotive functional safety ArterisIP ncore resilience package neural networks

Arteris Ncore Cache Coherent Interconnect and FlexNoC IP are Licensed by ZTE

Leading Chinese systems manufacturer purchases multiple licenses for cache coherent interconnect IP and network-on-chip fabric IP

CAMPBELL, Calif. — March 14, 2017 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that the chip design division of ZTE has licensed the highly-configurable Arteris® Ncore™ cache coherent interconnect IP as well as the Arteris FlexNoC® interconnect IP for use in its advanced systems-on-chip (SoC).

We chose Arteris Ncore interconnect IP and Arteris FlexNoC IP after an extensive evaluation where we ascertained technology to address the optimal mixing of ARM- and PCIe-based traffic in complex embedded systems.


Mr. Yu Li, Vice President, ZTE

Topics: Arteris FlexNoC new product china Ncore

Arteris Announces PIANO™ 2.0 Automated Interconnect Timing Closure Technology

CAMPBELL, Calif. — March 8, 2017 — Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced its next generation automated interconnect timing solution – the PIANO 2.0 Timing Closure Package. PIANO 2.0 builds on customer silicon experience gathered with FlexNoC Physical package to automate interconnect timing closure for both cache coherent and non-coherent subsystems.

By applying PIANO 2.0 together with generated placement guides, Renesas was able to close the complex SoC development sooner than we expected. Renesas has been an early user of Arteris’ closure technology, and we plan to continue to use Arteris’ enhanced closure capabilities for our future SoC developments.


Horst Rieger, Manager, Design Services, European Technology Center, Renesas Electronics Europe

Topics: Arteris FlexNoC timing closure new product Ncore PIANO timing closure package

Arteris announces 9 new licensees, multiple interconnect IP product releases and profitable operation in 2016

Ships major new technologies: Three releases of Ncore™ cache coherent interconnect and three releases of FlexNoC® non-coherent interconnect

CAMPBELL, Calif. — January 17, 2017 —  Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that it has added nine new licensees of Arteris interconnect IP for use in a variety of SoC applications. New Arteris customers added during 2016 include Kyocera, Movidius (acquired by Intel), Dream Chip Technologies, Istuary Innovation Group, Octasic, and four as-of-yet undisclosed customers. Arteris added nine new licensees in both 2014 and 2015.

I am happy to report that in 2016, Arteris earned nearly the same revenue and is almost the same size in terms of headcount as we were in the year prior to the 2013 Qualcomm transaction.


K. Charles Janac, President and CEO, Arteris

Topics: new customer new product arteris growth