Arteris Press Releases

Arteris IP and Synopsys Accelerate the Optimization of Heterogeneous Multicore Neural Network Systems-on-Chip

Ncore Cache Coherent Interconnect IP and Synopsys Platform Architect fast-tracks integration for autonomous driving and artificial intelligence (AI) markets

CAMPBELL, Calif. — January 30, 2018 — Arteris IP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced the integration of its Ncore Cache Coherent IP with the Synopsys® Platform Architect™ virtual prototyping solution to provide designers of neural network and autonomous driving SoCs with the ability to analyze system-level performance and power consumption earlier in the design cycle for their next-generation multicore architectures.

Combining Platform Architect and Ncore System models provides designers with the ability to analyze and optimize an entire heterogeneous multicore SoC architecture before RTL is available.


Eshel Haritan, Vice President of R&D, Verification Group, Synopsys

Topics: Synopsys Ncore artificial intelligence neural network Platform Architect SystemC ncore cache coherent interconnect

Arteris Delivers FlexNoC Physical™ Interconnect IP to Accelerate SoC Layout

New version improves SoC designer productivity, provides foundation for future technologies

CAMPBELL, California — April 22, 2015 — Arteris Inc., the inventor and only supplier of silicon-proven commercial network-on-chip (NoC) interconnect IP solutions,  today announced availability of Arteris FlexNoC Physical interconnect IP, a breakthrough that accelerates system-on-chip (SoC) physical design.

Arteris is solving an important set of back-end problems with technology that works earlier in the SoC design flow. FlexNoC Physical IP has the potential to significantly decrease timing issues experienced in the layout stage, reducing P&R iterations and engineering change orders (ECOs) and saving cost and schedule time.


Mike Demler, Senior AnalystThe Linley Group

Arteris FlexNoC Physical has the promise to improve layout productivity by providing Synopsys tools, such as Design Compiler Graphical and IC Compiler II, with improved timing closure information and more accurate RTL data. We look forward to working with mutual customers to validate these propositions.


Bijan Kiani, Vice President of Marketing, Design GroupSynopsys

Topics: Synopsys timing closure place and route new product Arteris FlexNoC Physical