Danube Network-on-Chip
Intellectual Property Library

The Danube Network-On-Chip Intellectual Property Library comprises configurable IP blocks that manage all on-chip communications between IP cores in System On Chip(SOC)designs.

Starting with the Arteris proprietary packet-based NoC Transaction and Transport Protocol (NTTP), users can flexibly implement any NoC topology required for communication between many different IP block types such as processors, DSPs, HW accelerators, I/O peripherals, memories, and so on, regardless of the socket interfaces the blocks use to communicate: AHB, AXI, OCP, or other proprietary interfaces.

Danube's complete range of flexible and highly custumizeable units, coupled with the benefits of packet-based transport, provide designers with the means to reach levels of performance and quality of service that far exceed the results obtained with traditional interconnect techniques.

Danube is an integral part of the Arteris NoCcompiler™ environment.

Key benefits

• Minimal wire and gate count required to handle on-chip communication.
• Easier backend phase with very few, exclusively point-to-point long wires to route.
• Choice of High performance or low gate count and power selection for each unit, as determined by user constraints.
• Scalable architecture supports an unlimited number of IP blocks connected to the NoC.

All units have been carefully optimized to provide high-speed operation, minimum latency and area.

Danube NoC IP library data sheet