NoCexplorer

NoCexplorer™ is a Network-On-Chip exploration and modeling tool for Arteris NoC IP products. This SoC architect’s software uses abstract models to perform in just a few hours the complex traffic analysis that is endemic in modern SoC design.

NoCexplorer is fully dedicated to modeling the behavior of an Arteris NoC, including packet transport, routing schemes, QOS mechanisms, buffering, rate adaptation, and so forth.

Using NoCexplorer, SoC architects can capture their system in the form of initiators and targets, and their traffic. They can then rapidly evaluate how variations to NoC topology affect overall system performance requirements.

NoCexplorer incorporates a unique throughput-accurate simulation engine that provides nearly instant reporting on congestion at shared resources, and the resulting system-level latency within the simulated NoC topology. This makes it possible to conduct fast-paced evaluations of alternative topologies until an optimal result is obtained.

Whether optimized for a specific application or pre-defined for a platform, the topology can then be implemented within the NoCcompiler environment by using Arteris NoC IP configurable libraries.

Key benefits

• NoCexplorer's level of abstraction provides a balanced tradeoff between speed and accuracy.
• Easy exploration of various NoC architectures for a given traffic.
• Easy analysis of NoC architectures under different traffics constraints.
• SystemC-based, making the resulting NoC model compatible with third-party ESL environments.

NoCexplorer data sheet