Arteris — The Products

Arteris NoC Solution consists of the Danube Intellectual Property Library and a suite of design tools for configuring and implementing the IP library as synthesizable RTL. The Danube Intellectual Property Library contains a set of configurable building blocks managing all on-chip communications between IP cores in SoC designs.

Configuring a Danube-based Network-On-Chip instance for integration within an application-specific SoC is a two-step process:

1. NoC topology creation
   Oriented to system-level communications and floorplanning requirements, the architecture tool NoCexplorer is used to create a NoC topology that meets cost, performance, and physical constraints.
2. NoC configuration, assembly, and design view creation
   In the NoCcompiler environment, selected Ateris NoC IP library units are configured and connected to match the topology obtained in the initial exploration step, in accordance with the specifications of the IP cores connected to the NoC. NoC design views, such as cycle-accurate SystemC models and synthesizable RTL, are then generated for simulation FPGA prototyping, or integration within the SoC using standard design flows.
   
   

Product backgrounder