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New version of Arteris NoC IP library and design
tools adds new low power NoC IP elements and software application debug;
Supports OCP 2.1 protocol
Paris, France — February
19, 2007 —
Arteris SA, a leading provider of Network-on-Chip
(NoC) solutions addressing challenges associated with on-chip
communications, today announced immediate availability of its Arteris
NoC Solution, Version 1.6. The latest release of the IP library and
accompanying tool set incorporates a range of customer-requested
features to improve the efficiency and ease-of-use of implementing NoCs
for multi-media, telecom infrastructure and wireless SoC designed in
leading-edge manufacturing processes down to 45-nanometer (nm). Key to
the release is a low-power version of the Arteris NoC IP library, aimed
specifically at demanding wireless and consumer applications.
Also, as part of this release, Arteris is announcing
support for the Open Core Protocol International Partnership (OCP-IP)
OCP 2.1 communication protocol.
Specific enhancements in the Arteris NoC 1.6 solution include:
- Low power version of the Arteris NoC IP library elements for
wireless mobile terminal applications and other low power applications.
Arteris has introduced hierarchical clock gating at the register or
module level, making it the lowest power interconnect available.
- New library units including multi-chip link for multi-die SoCs,
depleted switches, power isolator and support for firewall IPs. These
NoC elements IPs broaden the range of addressable architectures to
multi-die SoCs and SoCs with internal hardware security schemes.
- Support for multiple Quality of Service strategies, including
sophisticated memory scheduler, fixed priority, end-to-end dynamic
priority as well as best effort packet delivery.
- New Debug on Silicon features. These include a combination of IPs
and software tools that allows the use of a NoC as a logic analyzer
inside the SoC to debug software issues at the SoC emulation and
silicon prototype levels.
None of the new features degrade the wire efficiency
benefits of the Arteris NoC, which is one of the methodology's most
significant advantages.
"The Arteris NoC Solution 1.6 addresses critical
requirements such as
low power, support for multiple QoS strategies and the ability to debug
NoCs," said Charlie Janac, President and CEO of Arteris. "In addition,
with this release, we are expanding the range of SoC architectures that
can benefit from our on-chip communication approach."
"We are excited about the low power features of
the Arteris NoC Solution 1.6 release. On our M4 project for
development of next generation mobile application processors, we have
been able to very significantly reduce power utilization of our design
compared to earlier approaches," said Rudy Leuwerains, Vice President of
Application Architectures at IMEC.
The NoCexplorer 1.6 tool dramatically increase the efficiency of NoC
use by providing system architects with an easy way to analyze and
optimize the NoC interconnect based on data traffic at the earliest
stages of a SoC project. With a very light and synthetic traffic
modeling capability, architects can analyze system bandwidth, latency
and quality of service quickly and accurately. A SystemC output of an
NoC instance model is now available to be used in traditional ESL
tools including CoWare and ARM.
NoCcompiler, enhanced with a graphical capture and static connectivity
checks, allows easier NoC topology capture and configuration.
NoCcompiler automatically generates the RTL NoC instance specific to
each SoC or its derivative. Release 1.6 improvements also include more
checks in the automatically generated test suite.
SoC-level debug verification consumes an increasing portion of SoC
development time. The new on-silicon trace and debug features in
NoCprofiler ensure verification of SoC communication objectives have
been met once the NoC is in use in the SoC. Inserting a trace
mechanism in the Arteris NoC instance allows easier debugging of the
software running on SoC prototype or final chip.
Arteris broke new ground when it introduced the first commercially
available NoC solution in 2005. The Arteris NoC is a three-layer packet
switching network that operates inside complex SoCs. The solution uses
an innovative IP library of transport units, network interface units
and other soft IP blocks that allow Arteris customers to configure
their own flexible SoC communication subsystems. The NoC technology
improves upon traditional bus-based approaches that must be redesigned
for each different type of SoC configuration, and typically use more
wires, consume more power with lower performance, while often
increasing die size.
The Arteris NoC Solution integrates easily with existing EDA design
flows through RTL outputs in Verilog, VHDL and System C formats,
together with synthesis scripts. Important verification tools are
supported as well.
The Arteris NoC Solution 1.6 is available on either per project
license with a tapeout fee or royalty pricing models.
Arteris, SA, provides IPs and associated design
tools to improve performance of SoC architectures for Multimedia,
Telecom and Mobile applications compared to incumbent technologies.
Arteris Network-on-Chip solutions transport and manage the on-chip
communications within complex System-on-Chip (SoC) integrated circuits,
increasing performance, reducing number of global wires, with lower
power utilization while enabling the most complex, IP-laden designs.
It allows chip developers to implement efficient and high-performance
NoC designs, overcoming limitations of traditional layered or pipelined
bus-based architectures. Arteris technology is scaleable in terms of
the number of IP blocks designers can network, as well as with deep
submicron silicon manufacturing processes. The NoC solutions are
compatible with existing design flows and with IP interface standards.
The international company operates globally with
headquarters in Paris, France and offices in Boston and San Jose,
California. Arteris has raised more than $12 million in equity
investment from an international set of venture capitalists, including
Crescendo Ventures, Techno Venture Management and Ventech. More
information can be found at
http://www.arteris.com.
For more information, contact:
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