Arteris Network-On-Chip Technology

Networking has been proven in the computer systems arena to be an extremely effective means of managing communication in distributed systems. With the need to integrate an increasing variety of Intellectual Property (IP) blocks in a single System-on-Chip (SoC), communication management becomes critical when highly diversified functions must be supported. Traditionally, resource sharing of one form or another has been the only solution — typically derived from the shared bus architectures that are common to all processors. Arteris, however, offers a new approach to managing on-chip communication that resolves a number of key issues, including:

  • Limitations on the number of resources that can effectively share a bus.
  • Difficulties in implementing these resources in deep sub-micron process technologies.
  • Disparate traffic resulting from the integration of different functions, and the consequent need for Quality of Service (QoS).

    • To solve these challenges in complex SoC designs, a Network-on-Chip (NoC) must incorporate cutting-edge technology in order to meet system performance requirements and facilitate rapid design. In response to this need, Arteris produced the world's first commercial implementation of such technology.

    Instead of blindly adopting networking implementations used at the macro system level, Arteris technology borrows the most applicable concepts and applies them in a manner that is consistent with the constraints of semiconductor design. In particular, Arteris technology takes into account all the backend constraints inherent in deep submicron semiconductor technologies. This innovative approach incorporates the following key networking concepts:

  • Separate layers for communication protocol and hardware implementation, making independent optimization of each layer easier.
  • Packetization of transactions entering the NoC.
  • Stateless network.
  • Use of standardized packets for all information flow (data, control).
  • QoS-driven packet routing and arbitration.
  • Flexible NoC topologies to match total system performance needs.

    • Arteris solution reflects an in-depth understanding and integration of the constraints imposed by SoC applications and semiconductor processes. The solution ensures a balanced tradeoff between performance, area (gates), and latency. The following example is typical:

    Macro-level networks often serialize data to a single bit stream. This is impractical for silicon. In a typical NoC, data is carried in traditional byte-oriented 16, 32, 64, 128 or 256-bits widths in order to reach a required aggregate bandwidth while using clock rates that are compatible with semiconductor process and design flow requirements.

    In most complex SoC designs, latency and bandwidth are of greater or lesser importance depending on the nature of the IP block being serviced. The Arteris NoC has been carefully designed to provide low latency for blocks that require it, and optimal latency and bandwidth for the system as a whole.

    Arteris NoC functionality is organized in three tiers: the network transaction interface layer, the transport layer, and the physical implementation layer. This layered architecture is called NoC Transaction and Transport Protocol (NTTP), and provides unequaled on-chip communication performance, compared to traditional approaches.

    Transaction Layer

    At the Transaction layer level, Network Interface Units (NIU) manage communication with a connected IP core, and provide network services to that core. NIUs convert traditional load and store transactions into packets that are suitable for transport across the network. NIUs communicate with the network through an internal standard socket that matches the specific packet parameters being used on the network. At the periphery of the network, NIUs communicate with the attached IP cores via one of a number of standard IP sockets (interfaces), or through custom-built sockets developed by Arteris to meet specific customer needs

    Transport Layer

    The Transport layer deals exclusively with packets. Only a limited amount of information in packet headers needs to be examined in order to determine the required transport operations. The Transport layer can safely ignore the specifics of the transactions being managed at its own level, and does not need to take any action regarding those transactions. This simplifies the hardware required for switching and routing functions, and allows higher operating frequencies. Specific packet handling techniques guarantee quality of service or bandwidth. Optimization can be performed locally on specific routes, without affecting the NoC as a whole.

    Physical Layer

    The Physical layer defines how packets are actually transmitted between NoC units. Various link types with different capabilities, such as transport links, GALS links for longer distances, or Chip-to-Chip links, can be employed. Separate Transaction and Transport layers make it possible to change links, or their characteristics, without affecting the transport or transaction layers. Because all connections are point-to-point, high-fanout nets are prevented, thus providing better performance and easier routing. Compared to other interconnects, Arteris technology requires fewer nets, provides fully pipelinable units, and simplifies timing closure.

    Summary

    Through the packet-based transport and flexibility of adapting every path of the NoC topology to throughput, QOS and timing constraints, coupled with Network Interface Units that support all major IP interface standard, Arteris products provide designers with the ability to configure their SoC interconnect to match all of their constraints, from system-level down to physical implementation.